Method for manufacturing CMOS structure

    公开(公告)号:US10332804B2

    公开(公告)日:2019-06-25

    申请号:US14823224

    申请日:2015-08-11

    摘要: The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.

    LED driving circuit having SCR dimmer, circuit module and control method thereof

    公开(公告)号:US10285229B2

    公开(公告)日:2019-05-07

    申请号:US15935239

    申请日:2018-03-26

    IPC分类号: H05B33/08

    摘要: An apparatus can include: a bleeder circuit coupled to a DC bus of an LED driving circuit having an SCR dimmer; the bleeder circuit being configured to stabilize a voltage of the DC bus at a predetermined value by drawing a bleed current through a bleed path in a first mode, and to cut off the bleed path in a second mode; and a controller configured to control the bleeder circuit to be in the first mode before the SCR dimmer is turned on, and to switch to the second mode after the SCR dimmer is turned on, where the predetermined value is greater than zero.

    Ripple suppression circuit and light emitting diode driver

    公开(公告)号:US10264635B2

    公开(公告)日:2019-04-16

    申请号:US15968896

    申请日:2018-05-02

    发明人: Jian Deng

    摘要: A ripple suppression circuit for suppressing a ripple component in a drive current for an LED load includes: an output port connected to the LED load; a current filter circuit connected in series with the output port, and being configured to control the drive current based on an output voltage after a ripple component is filtered out, where the drive current is maintained as substantially stable; and a ripple shunt circuit connected between a drive current input terminal and a ground terminal, and being configured to shunt the drive current in response to the output voltage, where the output voltage is a voltage output from a power stage circuit that is coupled to the ripple suppression circuit.

    Multichannel constant current LED controlling circuit and controlling method

    公开(公告)号:US10187938B2

    公开(公告)日:2019-01-22

    申请号:US15587561

    申请日:2017-05-05

    IPC分类号: H05B33/08

    摘要: A multichannel constant current LED controlling circuit can include: (i) a control loop configured to generate a first control signal in accordance with a current feedback signal that represents a driving current flowing through an LED load, where the LED load comprises a plurality of LED strings coupled in series; (ii) a loop steady state network comprising a plurality of steady state holding components configured to hold a plurality of steady state control signals that correspond to a plurality of load states of the LED load, where when a state of the LED load varies, at least one of the steady state holding components is selected by the control loop to generate the first control signal; and (iii) a power switching transistor of a power stage circuit configured to generate a pseudo-constant output current to drive the LED load.

    Method of balancing battery power
    88.
    发明授权

    公开(公告)号:US10164440B2

    公开(公告)日:2018-12-25

    申请号:US15283551

    申请日:2016-10-03

    IPC分类号: H01M10/44 H02J7/00

    摘要: A method of balancing battery power can include: determining batteries to be balanced and directions of balance currents according to charge and discharge states and power states of the batteries, where each of the power states includes a state of charge, a remaining capacity, and a capacity to be charged; determining a reference of the balance current based on controlling temperatures of the batteries to be balanced to be lower than a temperature threshold when the SOCs of the batteries to be balanced are lower than a predetermined threshold; and balancing power of the batteries to be balanced according to the directions of the balance currents and the reference.

    Control circuit for interleaved switching power supply

    公开(公告)号:US10110131B2

    公开(公告)日:2018-10-23

    申请号:US14525876

    申请日:2014-10-28

    发明人: Feng Yu Chen Zhao

    IPC分类号: H02M3/158

    摘要: In one embodiment, a control circuit configured for an interleaved switching power supply, can include: (i) a feedback compensation signal generation circuit configured to sample an output voltage of the interleaved switching power supply, and to generate a feedback compensation signal; (ii) a first switch control circuit configured to compare a voltage signal indicative of an inductor current in the first voltage regulation circuit against the feedback compensation signal, and to control a first main power switch in the first voltage regulation circuit; and (iii) a second switch control circuit configured to turn on a second main power switch in the second voltage regulation circuit after half of a switching cycle after the first main power switch is turned on, and to regulate an on time of the second main power switch.

    Control circuit, control method and flyback converter

    公开(公告)号:US10097076B2

    公开(公告)日:2018-10-09

    申请号:US15673055

    申请日:2017-08-09

    摘要: In one embodiment, a control circuit can include: a voltage feedback circuit configured to obtain a voltage feedback signal that represents an output voltage of the power stage circuit; a set signal generator configured to output a set signal when a secondary current crosses zero or a voltage sampling signal reaches a valley value; a reset signal generator configured to output a reset signal in a constant on time mode when the voltage feedback signal is greater than a first voltage threshold value, and to output the reset signal in a peak current mode when the voltage feedback signal is less than the first voltage threshold value; and a logic circuit configured to activate a switching control signal according to the set signal, and to deactivate the switching control signal according to the reset signal.