公开(公告)号：US06703314B2

公开(公告)日：2004-03-09

申请号：US10308139

申请日：2002-12-03

Applicant: Sung-Kwon Lee ,  Sang-Ik Kim ,  Chang-Youn Hwang ,  Weon-Joon Suh ,  Min-Suk Lee

Inventor： Sung-Kwon Lee ,  Sang-Ik Kim ,  Chang-Youn Hwang ,  Weon-Joon Suh ,  Min-Suk Lee

IPC: H01L21302

CPC classification number: H01L21/76897 ,  H01L21/31116 ,  H01L21/7682

Abstract: Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.

Abstract translation: 提供一种用于形成可以最小化栅电极和硬掩模的损耗的半导体器件的自对准接触（SAC）的方法。 该方法包括以下步骤：提供其上形成有多个导电图案的半导体衬底; 沿着衬底上的导电图案的轮廓形成第一绝缘层; 在所述基板上形成第二绝缘层，同时在所述导电图案之间形成空隙; 在所述第一绝缘层上形成第三绝缘层; 以及形成通过蚀刻所述第三绝缘层和覆盖所述空隙的所述第二绝缘层而在所述导电图案之间暴露所述基板的表面的接触孔。