公开(公告)号：US20080220579A1

公开(公告)日：2008-09-11

申请号：US11683174

申请日：2007-03-07

Applicant: Rohit PAL ,  David BROWN ,  Scott LUNING

Inventor： Rohit PAL ,  David BROWN ,  Scott LUNING

IPC: H01L21/336 ,  H01L29/94

CPC classification number: H01L29/0847 ,  H01L21/31662 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848

Abstract: According to a method for fabricating a stress enhanced MOS device having a channel region at a surface of a semiconductor substrate, first and second trenches are etched into the semiconductor substrate, the first trench having a first side surface, and the second trench having a second side surface. The first and second side surfaces are formed astride the channel region. The first and second side surfaces are then oxidized in a controlled oxidizing environment to thereby grow an oxide region. The oxide region is then removed, thereby repositioning the first and second side surfaces closer to the channel region. With the first and second side surfaces repositioned, the first and second trenches are filled with SiGe.

Abstract translation: 根据用于制造在半导体衬底的表面具有沟道区的应力增强型MOS器件的方法，第一和第二沟槽被蚀刻到半导体衬底中，第一沟槽具有第一侧表面，并且第二沟槽具有第二沟槽 侧面。 第一和第二侧表面跨越通道区域形成。 然后将第一和第二侧表面在受控的氧化环境中氧化，从而生长氧化物区域。 然后去除氧化物区域，从而将第一和第二侧表面重新定位成更靠近沟道区域。 在第一和第二侧表面重新定位时，第一和第二沟槽被填充有SiGe。

公开(公告)号：US20080142835A1

公开(公告)日：2008-06-19

申请号：US11611784

申请日：2006-12-15

Applicant: Igor Peidous ,  Rohit Pal

Inventor： Igor Peidous ,  Rohit Pal

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L29/78687 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.

Abstract translation: 提供了一种应力增强型MOS晶体管及其制造方法。 提供了一种绝缘体上半导体结构，其包括具有第一表面的半导体层。 应变诱导外延层被覆盖地沉积在第一表面上，然后可用于产生覆盖在第一表面上的源极区域和漏极区域。