ELECTRONIC DEVICE AND BATTERY CONTROL METHOD

    公开(公告)号:US20250096583A1

    公开(公告)日:2025-03-20

    申请号:US18965639

    申请日:2024-12-02

    Inventor: Hyungwook CHOI

    Abstract: This electronic device may comprise: a first battery cell and a second battery cell connected in series to the first battery cell; a charging circuit configured to supply power of a first specified voltage from the outside to the first battery cell and the second battery cell; and at least one processor, comprising processing circuitry, individually and/or collectively, configured to control an overcharging protection operation voltage of the first battery cell and the second battery cell to a second specified voltage, wherein at least one processor, individually and/or collectively, is configured to; identify the voltage of the first battery cell and the voltage of the second battery cell while the first battery cell and the second battery cell are charged using the power of the first specified voltage; accumulate the number of times of overcharging protection operation for a battery cell having a voltage higher than the second specified voltage, based on at least one voltage among the voltage of the first battery cell and the voltage of the second battery cell being greater than the second specified voltage; and set an overcharging protection operation voltage for a battery cell having a voltage greater than the second specified voltage as a third specified voltage less than the second specified voltage, based on the number of times of the overcharging protection operation for the battery cell having a voltage greater than the second specified voltage reaches a specified number of times.

    ANTENNA ARRAY WITH PARTIALLY REFLECTIVE DEPOLARIZING METASURFACE

    公开(公告)号:US20250096483A1

    公开(公告)日:2025-03-20

    申请号:US18970093

    申请日:2024-12-05

    Abstract: The disclosure relates to radio engineering, and more specifically, to a wide scan angle antenna array. Technical result consists in expanding the scanning range, increasing the efficiency of the antenna array and reducing losses. Antenna array is provided. The antenna array includes a plurality of antenna array elements, and a metasurface disposed above the antenna array, wherein the metasurface is a dielectric layer having, on a first side thereof, conductive elements configured to reflect part of radiation of the antenna array; the distance between the antenna array and the metasurface is based on an integer number of half wavelengths, an operating wavelength of the antenna array in a medium in the space between the antenna array and the metasurface, and a predetermined scanning angle of the antenna array.

    INTEGRATED VOLTAGE REGULATOR (IVR) PACKAGE INCLUDING INDUCTOR AND CAPACITOR AND IVR SYSTEM PACKAGE INCLUDING THE IVR PACKAGE

    公开(公告)号:US20250096211A1

    公开(公告)日:2025-03-20

    申请号:US18963643

    申请日:2024-11-28

    Abstract: Provided are an integrated voltage regulator (IVR) package with a minimized size including one or more inductors and one or more capacitors together with an IVR chip and improving characteristics of a voltage regulator (VR), and an IVR system package including the IVR package. The IVR package includes a package substrate, a stacked structure mounted on the package substrate and having a stack structure in which a passive device chip including one or more capacitors and an IVR chip including a voltage regulator are stacked, and an intermediate substrate disposed on the package substrate in a structure surrounding the stacked structure, the intermediate substrate including vias therein. The one or more inductors are included in the stacked structure or the intermediate substrate.

    SEMICONDUCTOR PACKAGE
    85.
    发明申请

    公开(公告)号:US20250096158A1

    公开(公告)日:2025-03-20

    申请号:US18966367

    申请日:2024-12-03

    Inventor: Jongyoun KIM

    Abstract: A semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion. A first conductive barrier layer surrounds side surfaces of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.

    SEMICONDUCTOR PACKAGE
    86.
    发明申请

    公开(公告)号:US20250096099A1

    公开(公告)日:2025-03-20

    申请号:US18751036

    申请日:2024-06-21

    Abstract: A semiconductor package may include a lower redistribution structure having a lower redistribution layer, a lower chip structure on the lower redistribution structure, the lower chip structure including a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a plurality of first posts on a side of the second semiconductor chip and electrically connected to the first semiconductor chip, and a first encapsulant covering the first semiconductor chip, the second semiconductor chip, and the plurality of first posts, a plurality of second posts on a side of the lower chip structure and electrically connected to the lower redistribution layer, a second encapsulant covering the lower chip structure and each of the plurality of second posts, connection vias passing through a portion of the second encapsulant, and electrically connected to the plurality of first posts, and an upper redistribution structure on the second encapsulant.

    MODULE TRAY FOR SEMICONDUCTOR DEVICE

    公开(公告)号:US20250096024A1

    公开(公告)日:2025-03-20

    申请号:US18962104

    申请日:2024-11-27

    Inventor: Taegeon KIM

    Abstract: A module tray for a semiconductor device includes a base plate, first and second sidewalls extending in a vertical direction from opposite sides of the base plate to define an accommodation space, a dividing wall extending in the vertical direction from the base plate between the first and second sidewalls, first to fourth fastening guides with first to fourth fastening grooves, respectively, on inner surfaces of the first and second sidewalls and opposite side surfaces of the dividing wall, and first to fourth guide grooves on the inner surfaces of the first and second sidewalls and the opposite side surfaces of the dividing wall, respectively, the first to fourth guide grooves having curved concave shapes, and an upper end portion of each of the first to fourth fastening grooves gradually widening toward a top thereof.

    ELECTRONIC DEVICE FOR SELECTION AND CONTROL OF OBJECT ON BASIS OF CLASSIFICATION, AND METHOD THEREOF

    公开(公告)号:US20250095305A1

    公开(公告)日:2025-03-20

    申请号:US18962983

    申请日:2024-11-27

    Abstract: A wearable device includes: a display; and at least one processor, wherein the at least one processor is configured to: receive an input indicating selection of a first external electronic device and a second external electronic device among a plurality of external electronic devices viewable through the display; based on the input, identify third external electronic devices in a category including both the first external electronic device and the second external electronic device, and identify the first external electronic device and the second external electronic device along with the third external electronic devices; display a first visual object and a second visual object respectively indicating that the first external electronic device and the second external electronic device are selected; and display at least one third visual object guiding selection of at least one fourth external electronic device among the third external electronic devices.

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