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81.发明申请公开(公告)号：US20090063899A1
公开(公告)日：2009-03-05
申请号：US11849749
申请日：2007-09-04
IPC分类号： G06F11/07
CPC分类号： G06F11/10
摘要： In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.
摘要翻译： 在一个实施例中，处理器包括被配置为存储推测寄存器状态的第一寄存器文件，被配置为存储提交寄存器状态的第二寄存器文件，检查电路和控制单元。 第一个寄存器文件由第一个错误保护方案保护，第二个寄存器文件由第二个错误保护方案保护。 耦合检查电路以响应于处理器选择要提交的第一指令，接收从第一寄存器文件读取的值和对应的一个或多个校验位以提交给第二寄存器堆。 检查电路被配置为响应于该值和校验位来检测该值中的错误。 耦合到检查电路，控制单元被配置为响应于由检查电路检测到的错误而引起第一指令的再次执行。
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公开(公告)号：US07295672B2
公开(公告)日：2007-11-13
申请号：US10617632
申请日：2003-07-11
IPC分类号： H04L9/00
CPC分类号： H04L9/065 , H04L2209/125
摘要： A method and apparatus for encrypting information. In one embodiment, a method for encrypting information includes obtaining a value A from an array having a plurality of values and determining a value B based on the value A in a first pipeline stage. In a second pipeline stage, a value V may be determined from the value A and the value B. The value V may then be exclusive ORed (XORed) with a data value that forms a portion of the information being encrypted. A first logic unit may include the first pipeline stage, while a second logic unit may include the second pipeline stage. The array may be stored in a plurality of flip-flops in one embodiment, or may be stored in one or more register files in a second embodiment. The method and apparatus may be used for decrypting information as well.
摘要翻译： 一种用于加密信息的方法和装置。 在一个实施例中，用于加密信息的方法包括从具有多个值的阵列中获得值A，并且基于第一流水线级中的值A来确定值B. 在第二流水线阶段，可以从值A和值B确定值V.然后，值V可以与形成被加密的信息的一部分的数据值异或（异或）。 第一逻辑单元可以包括第一流水线级，而第二逻辑单元可以包括第二流水线级。 在一个实施例中，阵列可以存储在多个触发器中，或者可以在第二实施例中存储在一个或多个寄存器文件中。 该方法和装置也可用于解密信息。
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公开(公告)号：US5553015A
公开(公告)日：1996-09-03
申请号：US228480
申请日：1994-04-15
CPC分类号： G06F7/483 , G06F7/4991
摘要： A processing system that determines whether an underflow or overflow condition has occurred concurrently with the determination of the floating point exponent result uses a group of latched constants which can be added to the intermediate exponent and the exponent adjust to determine out of range conditions for all cases. The appropriate one of these latched constants (exponent range check values; exp.sub.-- range.sub.-- chk) are added to the exp.sub.-- int and exp.sub.-- adjust to give a value that will vary based on whether the exp.sub.-- result is out of range, or not. Different exp.sub.-- range.sub.-- chk values are used for underflow single precision, underflow double precision, overflow single precision and overflow double precision. The sum of these three values (exp.sub.-- int, exp.sub.-- adj, exp.sub.-- range.sub.-- chk) will yield a binary number having a most significant bit (MSB) that is dependent upon the exp.sub.-- result value. More particularly, the MSB will be a logical 1 when an out of range condition has occurred and a logical 0 for normal in range exponent results.
摘要翻译： 确定下溢或溢出条件是否与浮点指数结果的确定同时发生的处理系统使用一组可被添加到中间指数的锁存常数，并且指数调整以确定所有情况的超出范围条件 。 这些被锁存的常数（指数范围检查值; exp-range-chk）中适当的一个被添加到exp-int和exp-adjust中，以给出将根据exp-result超出范围而变化的值，或者 不。 不同的exp-range-chk值用于下溢单精度，下溢双精度，溢出单精度和溢出双精度。 这三个值（exp-int，exp-adj，exp-range-chk）的和将产生一个具有最高有效位（MSB）的二进制数，这取决于exp结果值。 更具体地说，当超出范围条件已经发生时，MSB将是逻辑1，并且在正常范围指数结果中为逻辑0。
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公开(公告)号：US5384723A
公开(公告)日：1995-01-24
申请号：US205123
申请日：1994-02-28
摘要： A method and apparatus for performing normalization of floating point numbers using a much smaller width register than would normally be required for the data operands which can be processed. As the registers are smaller, the number of circuits required to achieve the normalization is reduced, resulting in a decrease in the chip area required to perform such operation. The normalization circuitry was streamlined to efficiently operate on the more prevalent type of data being presented to the floating point unit. Data types and/or operations which statistically occur less frequently require multiple cycles of the normalization function. It was found that for the more prevalent data types and/or operations, the width of the registers required was substantially less than the width required for the less frequent data types and/or operations. Instead of expanding the register width to accommodate these lesser occurrences, the data is broken into smaller portions and normalized using successive cycles of the normalization circuitry. Thus, by sacrificing speed for the lesser occurring events, a significant savings was realized in the number of circuits required to implement normalization. As the slower speed operations occur infrequently, the overall performance of the normalization function is minimally impacted. Thus, considerable savings in integrated circuit real estate is achieved with minimal impact to the overall throughput of the system.
摘要翻译： 一种方法和装置，用于使用比可以处理的数据操作数通常要求的更小的宽度寄存器来执行浮点数的归一化。 由于寄存器较小，实现归一化所需的电路数量减少，导致执行此类操作所需的芯片面积减少。 归一化电路被简化以有效地对呈现给浮点单元的更普遍类型的数据进行操作。 统计上发生较少频率的数据类型和/或操作需要标准化功能的多个周期。 已经发现，对于更普遍的数据类型和/或操作，所需寄存器的宽度远小于较不频繁的数据类型和/或操作所需的宽度。 代替扩展寄存器宽度以适应这些较小的出现，数据被分解成更小的部分，并使用归一化电路的连续周期进行归一化。 因此，通过牺牲较小的事件的速度，实现标准化所需的电路数量实现了显着的节省。 由于较慢的速度操作不频繁发生，所以归一化功能的整体性能受到最小的影响。 因此，实现集成电路空间的可观节省，对系统的整体吞吐量的影响最小。
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