公开(公告)号：US20190220282A1

公开(公告)日：2019-07-18

申请号：US16368288

申请日：2019-03-28

Applicant: Google LLC

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein ,  Qiuling Zhu

IPC: G06F9/38 ,  G06F9/30 ,  H04N3/14 ,  G06T1/20 ,  G06F15/80

Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

公开(公告)号：US10185560B2

公开(公告)日：2019-01-22

申请号：US15591955

申请日：2017-05-10

Applicant: Google LLC

Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

IPC: G06F9/30 ,  G06F7/57 ,  G06F15/80

Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

公开(公告)号：US10095492B2

公开(公告)日：2018-10-09

申请号：US15591960

申请日：2017-05-10

Applicant: Google LLC

Inventor： Albert Meixner

IPC: G06F9/45 ,  G06F8/41 ,  G06F9/30

Abstract: A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.

公开(公告)号：US20180234653A1

公开(公告)日：2018-08-16

申请号：US15946095

申请日：2018-04-05

Applicant: Google LLC

Inventor： Albert Meixner ,  Daniel Frederic Finchelstein ,  David Patterson ,  William R. Mark ,  Jason Rupert Redgrave ,  Ofer Shacham

IPC: H04N5/374 ,  H04N5/341 ,  G06F5/01 ,  G06F17/16 ,  G06F12/02 ,  G06T1/20

CPC classification number: H04N5/3742 ,  G06F5/015 ,  G06F12/0207 ,  G06F17/16 ,  G06T1/20 ,  H04N5/341

Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.