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公开(公告)号:US06627105B1
公开(公告)日:2003-09-30
申请号:US09722110
申请日:2000-11-27
申请人: Tae Kyu Kim , Jum Soo Kim , Mun Hwa Lee , Jong Woo Kim
发明人: Tae Kyu Kim , Jum Soo Kim , Mun Hwa Lee , Jong Woo Kim
IPC分类号: C04B35491
CPC分类号: C01G25/006 , C01P2002/72 , C04B35/491 , C04B2235/3249 , C04B2235/3251 , C04B2235/3296 , C04B2235/449 , C04B2235/5204 , H01L41/187
摘要: There is disclosed a method of fabricating a piezoelectric ceramics. It can obtain a small grain size and a fine grain phase by forming a combined powder being major components, stirring the combined powder with (COOH)2 water solution, dropping a Pb(NO3)2 water solution into the stirred powder, and forming a PZT powder by calcinations and sintering processes.
摘要翻译: 公开了一种制造压电陶瓷的方法。 通过形成作为主要成分的组合粉末,用(COOH)2水溶液搅拌合并的粉末,将Pb(NO 3)2水溶液滴入搅拌粉末中,可以获得小粒径和细晶粒相,并形成 PZT粉末通过煅烧和烧结过程。
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公开(公告)号:US06381192B1
公开(公告)日:2002-04-30
申请号:US09722470
申请日:2000-11-28
申请人: Byung Jin Ahn , Sheung Hee Park , Min Kyu Kim , Jong Woo Kim
发明人: Byung Jin Ahn , Sheung Hee Park , Min Kyu Kim , Jong Woo Kim
IPC分类号: G11C800
摘要: An address buffer in a flash memory includes a buffer section for buffering external addresses to select specific sectors in the flash memory, a code storage section for storing a code to select a memory sector in the flash memory, a setting section for outputting internal addresses IA17˜IA17 selecting the memory sector, by using the code outputted from the code storage section and sector select addresses among the external addresses.
摘要翻译: 闪速存储器中的地址缓冲器包括用于缓冲外部地址以选择闪速存储器中的特定扇区的缓冲器部分,用于存储选择闪速存储器中的存储器扇区的代码的代码存储部分,用于输出内部地址IA17的设置部分 〜IA17通过使用从代码存储部分输出的代码和外部地址中的扇区选择地址来选择存储器扇区。
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83.
公开(公告)号:US5926435A
公开(公告)日:1999-07-20
申请号:US843
申请日:1997-12-30
申请人: Kee Woo Park , Jong Woo Kim
发明人: Kee Woo Park , Jong Woo Kim
IPC分类号: G11C7/00 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C8/00
CPC分类号: G11C7/1093 , G11C11/4076 , G11C7/1078 , G11C7/22
摘要: A power consumption saving apparatus for semiconductor memory devices such as DRAM's, which is configured to preferentially latch a clock signal and a chip selection signal over other input command signals so that latch circuits for latching the input command signals are controlled in accordance with the clock signal and chip selection signal, thereby saving power consumption occurring in input latches not selected. The apparatus includes an input latch as a latch control circuit for preferentially latching a clock signal and a chip selection signal and outputting the latched signals as a control signal for controlling latch circuits.
摘要翻译: 一种用于诸如DRAM的半导体存储器件的功耗节省装置,其被配置为优先地锁存时钟信号和芯片选择信号超过其他输入命令信号,从而根据时钟信号来控制用于锁存输入命令信号的锁存电路 和芯片选择信号,从而节省了未被选择的输入锁存器中发生的功耗。 该装置包括输入锁存器作为锁存控制电路,用于优先锁存时钟信号和芯片选择信号,并输出锁存信号作为控制锁存电路的控制信号。
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