公开(公告)号：US6023287A

公开(公告)日：2000-02-08

申请号：US805225

申请日：1997-02-24

申请人： Yasuhiro Kimura ,  Tatsunori Kanai ,  Toshio Shirakihara ,  Toshihiko Shimokawa ,  Hiroshi Yao

发明人： Yasuhiro Kimura ,  Tatsunori Kanai ,  Toshio Shirakihara ,  Toshihiko Shimokawa ,  Hiroshi Yao

IPC分类号： H04H20/38 ,  H04H20/76 ,  H04H60/48 ,  H04H60/65 ,  H04N7/173 ,  H04N7/00

CPC分类号： H04H60/48 ,  H04H20/38 ,  H04H20/76 ,  H04H60/65 ,  H04N21/21805 ,  H04N21/44016 ,  H04N21/4622 ,  H04N21/47205 ,  H04N21/84 ,  H04N5/44 ,  H04N7/002

摘要： A scheme for image selection in an image transmission system for transmitting images from an image source to an image display device, capable of eliminating a need for the viewer to select the desired image by actually watching individual images and easily selecting the desired image in which a specific desired target of the viewer is shown. Feature information for identifying targets shown in each image is obtained, while a desired feature information for identifying a desired target specified by the viewer is entered. Then, the desired image which contains the desired target specified by the viewer is selected according to the obtained feature information and the entered desired feature information. The feature information may be obtained by recognizing targets shown in each image provided by the image source, or may be generated in advance in correspondence to images provided by the image source.

摘要翻译： 一种用于将图像从图像源发送到图像显示装置的图像传输系统中的图像选择方案，其能够通过实际观看各个图像来消除对观众选择所需图像的需要，并且容易地选择期望的图像，其中 显示观察者的特定期望目标。 获得用于识别每个图像中所示的目标的特征信息，同时输入用于识别由观看者指定的期望目标的期望特征信息。 然后，根据所获得的特征信息和输入的期望特征信息来选择包含由观看者指定的期望目标的期望图像。 可以通过识别由图像源提供的每个图像中所示的目标来获得特征信息，或者可以相应于图像源提供的图像预先生成特征信息。

公开(公告)号：US5864679A

公开(公告)日：1999-01-26

申请号：US859724

申请日：1997-05-21

申请人： Tatsunori Kanai ,  Takeshi Yokokawa

发明人： Tatsunori Kanai ,  Takeshi Yokokawa

IPC分类号： G06F9/46 ,  G06F15/00

CPC分类号： G06F9/466 ,  Y10S707/99933

摘要： A multiple processor transaction processing system having both a transaction routing unit for routing each transaction generated by the transaction source to one of the transaction processors, and a data arrangement unit for determining data arrangement of the data to be used in processing the transactions by the transaction processors. The transaction routing unit routes each transaction to one of the transaction processors according to the feature parameters extracted from each transaction and the processing history information for past transactions processed by the transaction processors. The data arrangement unit determines a new data arrangement of the data in the data storage regions according to a data storage information indicating original arrangement of the data in the data storage regions and the correlation information indicating all sets of data which are accessed together in each series processing carried out by the transaction processors.

摘要翻译： 一种具有交易路由单元的多处理器交易处理系统，用于将由交易源产生的每个交易路由到交易处理器之一，以及数据排列单元，用于确定用于通过交易处理交易的数据的数据排列 处理器。 交易路由单元根据从每个交易提取的特征参数以及由交易处理器处理的过去交易的处理历史信息将每个交易路由到交易处理器之一。 数据排列单元根据指示数据存储区域中的数据的原始排列的数据存储信息和指示在每个系列中一起访问的所有数据集的相关信息，确定数据存储区域中的数据的新数据排列 处理由交易处理器执行。

公开(公告)号：US5778179A

公开(公告)日：1998-07-07

申请号：US827895

申请日：1997-04-07

申请人： Tatsunori Kanai ,  Toshio Shirakihara

发明人： Tatsunori Kanai ,  Toshio Shirakihara

IPC分类号： G06F12/00 ,  G06F15/16 ,  G06F15/17 ,  G06F15/163

CPC分类号： G06F15/17

摘要： A flexible distributed processing system capable of dealing with sophisticated conditions for selecting a server process. In the system, each of the services provided by all server processes is registered in the service manager in correspondence with an executability condition for judging whether each service is executed, such that the service manager selects one of the server processes which is providing the desired service indicated by the inquiry transmitted from the client process and which is judged to be executable according to the executability condition registered at the service manager, and the client process requests the desired service the selected one of the server processes. The system can utilize a transaction processing for a nested transaction in which a commit processing for the processes of the sub-transactions which are incapable of executing the nested transaction, is completed concurrently with a completion of the commit processing for the top level transaction.

摘要翻译： 灵活的分布式处理系统，能够处理选择服务器进程的复杂条件。 在系统中，所有服务器进程提供的每个服务都与服务管理器中的每个服务对应的可执行条件相对应，用于判断每个服务是否被执行，从而服务管理器选择提供所需服务的服务器进程之一 由从客户端进程发送的查询指示，并且根据在服务管理器处登记的可执行性条件被判断为可执行，并且客户端进程向所选择的一个服务器进程请求期望的服务。 系统可以利用嵌套事务的事务处理，其中对于不能执行嵌套事务的子事务的处理的提交处理与顶层事务的提交处理的完成同时完成。

公开(公告)号：US08271853B2

公开(公告)日：2012-09-18

申请号：US12393256

申请日：2009-02-26

申请人： Tatsunori Kanai ,  Yutaka Yamada

发明人： Tatsunori Kanai ,  Yutaka Yamada

IPC分类号： H03M13/00

CPC分类号： G06F11/1064

摘要： A cache memory has a data holding unit having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.

摘要翻译： 高速缓冲存储器具有数据保持单元，该数据保持单元具有多个高速缓存线，每条高速缓存行包括地址区，数据区和脏位，以及给予读取数据的控制器和指示是否执行了纠错的校正执行信号 对于读取数据，读取数据已从存储错误校正编码数据的存储器中读出，该数据还将与读取数据相对应的地址信息存储到多个高速缓存行中的任一个的地址区域中，将读取的数据存储到 数据区域，并且基于校正执行信号将预定值设置为脏位。

公开(公告)号：US08219767B2

公开(公告)日：2012-07-10

申请号：US12199111

申请日：2008-08-27

申请人： Kenichiro Yoshii ,  Hiroshi Yao ,  Tomohide Jokan ,  Tatsunori Kanai

发明人： Kenichiro Yoshii ,  Hiroshi Yao ,  Tomohide Jokan ,  Tatsunori Kanai

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F11/1441 ,  G06F1/30

摘要： A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.

摘要翻译： 信息处理装置包括：在上一次修改时，指示将存储的主存储单元的存储内容写入主存储单元的存储内容中的顺序号，用于识别是否回写到主存储器单元 从存储在备用存储器单元中的备份数据需要存储在序列号存储单元中的序列号。 信息处理装置选择包括表示完全进行写入的完整性验证数据的备份数据。 信息处理装置提取所选择的备份数据中包含的原始数据和写入目的地地址，并将原始数据和从备份数据提取的写入地址的原始数据写入主存储器单元的存储区域， 由写入目标地址指示。

公开(公告)号：US08108941B2

公开(公告)日：2012-01-31

申请号：US11350798

申请日：2006-02-10

申请人： Tatsunori Kanai

发明人： Tatsunori Kanai

IPC分类号： H04N7/16

CPC分类号： G06F21/445 ,  G06F21/31 ,  G06F21/554 ,  G06F21/81 ,  G06F2221/2129

摘要： A processor, connected to a non-volatile memory storing first memory authentication information for authentication of the non-volatile memory, the processor includes an operation unit configured to perform an operation utilizing information stored in the non-volatile memory; an authentication memory formed integrally with the operation unit, and storing second memory authentication information for authentication of the non-volatile memory; an authentication information acquiring unit configured to acquire the first memory authentication information from the non-volatile memory; a memory authenticating unit configured to compare the first memory authentication information and the second memory authentication information to authenticate the non-volatile memory; and a memory access controlling unit configured to permit an access to the non-volatile memory when the memory authenticating unit succeeds in authentication.

摘要翻译： 一种处理器，连接到存储用于非易失性存储器的认证的第一存储器认证信息的非易失性存储器，所述处理器包括：操作单元，被配置为使用存储在所述非易失性存储器中的信息执行操作; 认证存储器，与所述操作单元一体地形成，并存储用于所述非易失性存储器的认证的第二存储器认证信息; 认证信息获取单元，被配置为从所述非易失性存储器获取所述第一存储器认证信息; 存储器认证单元，被配置为比较所述第一存储器认证信息和所述第二存储器认证信息以认证所述非易失性存储器; 以及存储器访问控制单元，被配置为当所述存储器认证单元成功认证时允许对所述非易失性存储器的访问。

公开(公告)号：US07685599B2

公开(公告)日：2010-03-23

申请号：US10935188

申请日：2004-09-08

申请人： Tatsunori Kanai ,  Seiji Maeda ,  Hirokuni Yano ,  Kenichiro Yoshii

发明人： Tatsunori Kanai ,  Seiji Maeda ,  Hirokuni Yano ,  Kenichiro Yoshii

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F13/00 ,  H04L12/28

CPC分类号： G06F9/4881

摘要： An information processing system performs a plurality of tasks within a specific time interval. The system includes a bus, a plurality of processors which transfer data via the bus, and a unit for performing a scheduling operation of determining execution start timing of each of the tasks and at least one the processors which executes the tasks, based on cost information concerning a time required to perform each of the tasks and bandwidth information concerning a data transfer bandwidth required by each of the tasks, to perform the tasks within the specific time interval without overlapping execution terms of at least two tasks of the tasks, the two tasks requiring data transfer bandwidths not less than those of the others of the tasks.

摘要翻译： 信息处理系统在特定时间间隔内执行多个任务。 该系统包括总线，经由总线传送数据的多个处理器和用于执行确定每个任务的执行开始定时的调度操作的单元和至少一个执行任务的处理器，基于成本信息 关于执行每个任务所需的时间和与每个任务所需的数据传输带宽有关的带宽信息，以在特定时间间隔内执行任务而不重叠任务的至少两个任务的执行条件，这两个任务 要求数据传输带宽不低于其他任务的带宽。

公开(公告)号：US07657890B2

公开(公告)日：2010-02-02

申请号：US10808470

申请日：2004-03-25

申请人： Tatsunori Kanai ,  Seiji Maeda ,  Kenichiro Yoshii ,  Hirokuni Yano

发明人： Tatsunori Kanai ,  Seiji Maeda ,  Kenichiro Yoshii ,  Hirokuni Yano

IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F9/26

CPC分类号： G06F9/50 ,  G06F9/45533

摘要： A real-time processing system that executes a plurality of threads, each of the threads being a unit of execution of a real-time operation, comprises a plurality of processors, a unit which selects a tightly coupled thread group from among the threads based on coupling attribute information indicative of a coupling attribute between the threads, the tightly coupled thread group including a set of tightly coupled threads running in cooperation with each other, and a unit which performs a scheduling operation of dispatching the tightly coupled threads to several of the processors that are equal to the tightly coupled threads to simultaneously execute the tightly coupled threads by the several of the processors.

摘要翻译： 执行多个线程的实时处理系统，每个线程是执行实时操作的单元，包括多个处理器，一个单元，其基于以下方式从线程中选择紧密耦合的线程组： 耦合属性信息，指示线程之间的耦合属性，紧密耦合的线程组包括彼此协作运行的一组紧密耦合的线程;以及单元，执行调度操作以将紧密耦合的线程分派到若干处理器 这等于紧密耦合的线程，以同时由几个处理器执行紧密耦合的线程。

公开(公告)号：US20090319865A1

公开(公告)日：2009-12-24

申请号：US12393256

申请日：2009-02-26

申请人： Tatsunori Kanai ,  Yutaka Yamada

发明人： Tatsunori Kanai ,  Yutaka Yamada

IPC分类号： H03M13/09

CPC分类号： G06F11/1064

摘要： A cache memory has a data holding unit having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.

摘要翻译： 高速缓冲存储器具有数据保持单元，该数据保持单元具有多个高速缓存线，每条高速缓存行包括地址区，数据区和脏位，以及给予读取数据的控制器和指示是否执行了纠错的校正执行信号 对于读取数据，读取数据已从存储错误校正编码数据的存储器中读出，该数据还将与读取数据相对应的地址信息存储到多个高速缓存行中的任何一个的地址区域中，将读取的数据存储到 数据区域，并且基于校正执行信号将预定值设置为脏位。

公开(公告)号：US07464379B2

公开(公告)日：2008-12-09

申请号：US10902938

申请日：2004-08-02

申请人： Tatsunori Kanai ,  Seiji Maeda ,  Hirokuni Yano ,  Kenichiro Yoshii

发明人： Tatsunori Kanai ,  Seiji Maeda ,  Hirokuni Yano ,  Kenichiro Yoshii

IPC分类号： G06F9/46 ,  G06F1/04 ,  G06F1/12 ,  G06F15/16

CPC分类号： G06F9/4887 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

摘要： An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.

摘要翻译： 信息处理系统以特定的时间间隔周期性地执行实时操作。 该系统包括用于执行调度操作的单元，该调度操作将实时操作分配给处理器，以由处理器以特定时间间隔周期性地执行实时操作，用于计算实际的执行时间的比率的单元 基于具体的时间间隔和关于处理器以第一操作速度进行实时操作所需的时间的成本信息，处理器以第一操作速度执行的时间操作，以及用于执行 操作速度控制操作以在低于第一操作速度的第二操作速度下操作处理器，基于所计算的比率来确定第二操作速度。