公开(公告)号：US10996968B2

公开(公告)日：2021-05-04

申请号：US15529426

申请日：2014-11-24

Applicant: INTEL CORPORATION

Inventor： Yaozu Dong ,  Kun Tian

IPC: G06T15/00 ,  G06F9/455 ,  G06T1/20 ,  G06T1/60

Abstract: Methods, software, and apparatus for application transparent, high available GPU computing with VM checkpointing. The guest access of certain GPU resources, such as MMIO resources, are trapped to keep a copy of guest context per semantics, and/or emulate the guest access of the resources prior to submission to the GPU, while other commands relating to certain graphics memory address regions are trapped before being passed through to the GPU. The trapped commands are scanned before submission to predict: a) potential to-be-dirtied graphics memory pages, and b) the execution time of intercepted commands, so the next checkpointing can be aligned to a predicted execution time. The GPU internal states are drained by flushing internal context/tlb/cache, at the completion of submitted commands, and then a snapshot of the vGPU state is taken, based on tracked GPU state, GPU context (through GPU-specific commands), detected dirty graphics memory pages and predicted to-be dirtied graphics memory pages.

公开(公告)号：US20200258191A1

公开(公告)日：2020-08-13

申请号：US16791514

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/60 ,  G06T1/20

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US10572288B2

公开(公告)日：2020-02-25

申请号：US15576835

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Kun Tian ,  Yao Zu Dong

IPC: G06F9/455 ,  G06F9/54 ,  G06F12/10

Abstract: An apparatus and method are described for efficient inter-virtual machine (VM) communication. For example, an apparatus comprises inter-VM communication logic to map a first specified set of device virtual memory addresses of a first VM to a first set of physical memory addresses in a shared system memory and to further map a second specified set of device virtual memory addresses of a second VM to the first set physical memory addresses in the shared system memory.

公开(公告)号：US10565127B2

公开(公告)日：2020-02-18

申请号：US15815511

申请日：2017-11-16

Applicant: Intel Corporation

Inventor： Yao Zu Dong ,  Kun Tian

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F12/109 ,  G06F12/02 ,  G06F9/455 ,  G06F9/50 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.

公开(公告)号：US10482567B2

公开(公告)日：2019-11-19

申请号：US16062603

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Zhiyuan Lv ,  Kun Tian

IPC: G06T1/20 ,  G06F13/00 ,  G06F12/1009 ,  G06T1/60 ,  G06T15/00 ,  G06T15/80 ,  G06F12/14

Abstract: An apparatus and method are described for intelligent resource provisioning for shadow structures. For example, one embodiment of an apparatus comprises: graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames in a graphics memory address space; shadow structure management logic to reserve one or more shadow slots in the graphics memory address space in which to store shadow instances of different GPU contexts; and the shadow structure management logic to implement a partial shadowing policy for shadowing GPU contexts in the shadow slots, the partial shadowing policy based on characteristics of pages of the GPU contexts.

公开(公告)号：US10467048B2

公开(公告)日：2019-11-05

申请号：US15577041

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Yao Zu Dong ,  Kun Tian

IPC: G06F9/48 ,  G06F9/455

Abstract: Examples may include techniques for virtual machine (VM) migration. Examples may include selecting a VM for live migration from a source node to a destination node, predicting a time period associated with the live migration, and selecting another VM from which allocated source node bandwidth may borrowed to facilitate the live migration within the predicted time.

公开(公告)号：US10460417B2

公开(公告)日：2019-10-29

申请号：US16010692

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06F9/48 ,  G06F9/38 ,  G06T1/20 ,  G06F9/50

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.

公开(公告)号：US10452495B2

公开(公告)日：2019-10-22

申请号：US15576075

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Yao Zu Dong ,  Yunhong Jiang ,  Kun Tian

IPC: G06F11/14 ,  H04L1/08 ,  G06F9/54 ,  G06F11/16

Abstract: It includes techniques to provide for reliable primary and secondary containers arranged to separately execute an application that receives request packets for processing by the application. The request packets may be received from a client coupled with a server arranged to host the primary container or the secondary container. The client coupled with the server through a network. Coarse-grained lock-stepping (COLO) methods may be utilized to facilitate in providing the reliable primary and secondary containers.

公开(公告)号：US20190286479A1

公开(公告)日：2019-09-19

申请号：US16156550

申请日：2018-10-10

Applicant: Intel Corporation

Inventor： Kun Tian ,  Zhiyuan Lv ,  Yao Zu Dong

IPC: G06F9/48 ,  G06F9/455 ,  G06T1/20 ,  G06F9/50 ,  G06F9/52

Abstract: Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU.

公开(公告)号：US10375022B2

公开(公告)日：2019-08-06

申请号：US15677829

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Yaozu Dong ,  Kun Tian

IPC: G06F9/46 ,  H04L29/06 ,  H04L12/931 ,  G06F9/455

Abstract: An apparatus, system, method, and machine-readable medium are disclosed. In one embodiment the apparatus is a network interface controller that includes one virtual function owned by a virtual machine present in the computer system. The controller includes a simple filtering agent that is associated with the first virtual function. The agent enforces simple filter rules for received network packets. The simple filter rules are capable of blocking the network packets from reaching the virtual machine. The apparatus also includes another virtual function that is owned by a virtual machine monitor present in the computer system. The controller also includes a side bounce filtering agent to forward the first network packet to the second virtual function if the first packet is blocked by the at least one of the one or more simple filter rules.