公开(公告)号：US20230100328A1

公开(公告)日：2023-03-30

申请号：US17867371

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  David Andrew Roberts ,  Patrick Michael Sheridan ,  Lukasz Burzawa

IPC: G06F12/0882 ,  G06F12/06

Abstract: Disclosed in some examples are improved address prediction and memory preloading that leverages next-delta prediction and/or far-delta prediction for scheduling using a DNN. Previous memory access sequence data that identify one or more memory addresses previously accessed by one or more processors of a system may be processed and then converted into a sequence of delta values. The sequence of delta values are then mapped to one or more classes that are then input to a DNN. The DNN then outputs a predicted future class identifier sequence that represents addresses that the DNN predicts will be accessed by the processor in the future. The predicted future class identifier sequence is then converted back to a predicted delta value sequence and back into a set of one or more predicted addresses.

公开(公告)号：US20230031680A1

公开(公告)日：2023-02-02

申请号：US17931541

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/02 ,  G06F12/0802

Abstract: Described apparatuses and methods balance memory-portion accessing. Some memory architectures are designed to accelerate memory accesses using schemes that may be at least partially dependent on memory access requests being distributed roughly equally across multiple memory portions of a memory. Examples of such memory portions include cache sets of cache memories and memory banks of multibank memories. Some code, however, may execute in a manner that concentrates memory accesses in a subset of the total memory portions, which can reduce memory responsiveness in these memory types. To account for such behaviors, described techniques can shuffle memory addresses based on a shuffle map to produce shuffled memory addresses. The shuffle map can be determined based on a count of the occurrences of a reference bit value at bit positions of the memory addresses. Using the shuffled memory address for memory requests can substantially balance the accesses across the memory portions.

公开(公告)号：US20220276792A1

公开(公告)日：2022-09-01

申请号：US17663609

申请日：2022-05-16

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: Described apparatuses and methods control a voltage or a temperature of a memory domain to balance memory performance and energy use. In some aspects, an adaptive controller monitors memory performance metrics of a host processor that correspond to commands made to a memory domain of a memory system, including one operating at cryogenic temperatures. Based on the memory performance metrics, the adaptive controller can determine memory performance demand of the host processor, such as latency demand or bandwidth demand, for the memory domain. The adaptive controller may alter, using the determined performance demand, a voltage or a temperature of the memory domain to enable memory access performance that is tailored to meet the demand of the host processor. By so doing, the adaptive controller can manage various settings of the memory domain to address short- or long-term changes in memory performance demand.

公开(公告)号：US11409657B2

公开(公告)日：2022-08-09

申请号：US16928932

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0862 ,  G06F12/0891

Abstract: Described apparatuses and methods track access metadata pertaining to activity within respective address ranges. The access metadata can be used to inform prefetch operations within the respective address ranges. The prefetch operations may involve deriving access patterns from access metadata covering the respective ranges. Suitable address range sizes for accurate pattern detection, however, can vary significantly from region to region of the address space based on, inter alia, workloads produced by programs utilizing the regions. Advantageously, the described apparatuses and methods can adapt the address ranges covered by the access metadata for improved prefetch performance. A data structure may be used to manage the address ranges in which access metadata are tracked. The address ranges can be adapted to improve prefetch performance through low-overhead operations implemented within the data structure. The data structure can encode hierarchical relationships that ensure the resulting address ranges are distinct.

公开(公告)号：US20220188606A1

公开(公告)日：2022-06-16

申请号：US17120786

申请日：2020-12-14

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit (IC) device includes a first stack of IC dies connected to a plurality of second stacks of IC dies. The first stack has a first die of a memory controller and processing units of the Deep Learning Accelerator and at least one second die that is stacked on the first die to provide a first type of memory. Each of the second stacks has a base die and at least a third die and a fourth die having different types of memory. The base die has logic circuit configured to copy data within the same stack in response to commands from the memory controller and has a second type of memory usable as die cross buffer.

公开(公告)号：US20220188250A1

公开(公告)日：2022-06-16

申请号：US17682908

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski ,  Elliott Cooper-Balis

IPC: G06F13/16 ,  G06F3/06 ,  G06F1/324 ,  G06F1/10

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

公开(公告)号：US11354246B2

公开(公告)日：2022-06-07

申请号：US17135341

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0862 ,  G06F13/16

Abstract: Techniques for implementing and/or operating an apparatus, which includes a memory system coupled to a processing system via a memory bus. The memory system includes hierarchical memory levels and a memory controller. The memory controller receives a memory access request at least in part by receiving an address parameter indicative of a memory address associated with a data block from the memory bus during a first clock cycle and receiving a context parameter indicative of context information associated with current targeting of the data block from the memory bus during a second clock cycle, instructs the memory system to output the data block to the memory bus based on the memory address indicated in the address parameter, and predictively controls data storage in the hierarchical memory levels based at least in part on the context information indicated in the context parameter of the memory access request.

公开(公告)号：US11281604B2

公开(公告)日：2022-03-22

申请号：US16804895

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski ,  Elliott Cooper-Balis

IPC: G06F1/324 ,  G06F13/16 ,  G06F3/06 ,  G06F1/10

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

公开(公告)号：US20220058132A1

公开(公告)日：2022-02-24

申请号：US16997811

申请日：2020-08-19

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0895 ,  G06F12/0862

Abstract: Described apparatuses and methods partition a cache memory based, at least in part, on a metric indicative of prefetch performance. The amount of cache memory allocated for metadata related to prefetch operations versus cache storage can be adjusted based on operating conditions. Thus, the cache memory can be partitioned into a first portion allocated for metadata pertaining to an address space (prefetch metadata) and a second portion allocated for data associated with the address space (cache data). The amount of cache memory allocated to the first portion can be increased under workloads that are suitable for prefetching and decreased otherwise. The first portion may include one or more cache units, cache lines, cache ways, cache sets, or other resources of the cache memory.

公开(公告)号：US20220019537A1

公开(公告)日：2022-01-20

申请号：US16928932

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0862 ,  G06F12/0891

Abstract: Described apparatuses and methods track access metadata pertaining to activity within respective address ranges. The access metadata can be used to inform prefetch operations within the respective address ranges. The prefetch operations may involve deriving access patterns from access metadata covering the respective ranges. Suitable address range sizes for accurate pattern detection, however, can vary significantly from region to region of the address space based on, inter alia, workloads produced by programs utilizing the regions. Advantageously, the described apparatuses and methods can adapt the address ranges covered by the access metadata for improved prefetch performance. A data structure may be used to manage the address ranges in which access metadata are tracked. The address ranges can be adapted to improve prefetch performance through low-overhead operations implemented within the data structure. The data structure can encode hierarchical relationships that ensure the resulting address ranges are distinct.