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105 条记录 (耗时 0.027 秒)

    Body biasing for dynamic circuit
    82.
    发明申请
    Body biasing for dynamic circuit 审中-公开
    动态电路的主体偏置

    公开(公告)号：US20060132187A1

    公开(公告)日：2006-06-22

    申请号：US11018011

    申请日：2004-12-20

    申请人： James Tschanz ,  Ram Krishnamurthy ,  Siva Narendra ,  Vivek De

    发明人： James Tschanz ,  Ram Krishnamurthy ,  Siva Narendra ,  Vivek De

    IPC分类号： H03K19/096

    CPC分类号： H03K19/0963

    摘要： In some embodiments, a circuit is provided that comprises a dynamic circuit and a body bias circuit. The dynamic circuit has a keeper transistor. The body bias circuit is coupled to the keeper transistor and is configured to body bias the keeper transistor in accordance with a leakage associated with the dynamic circuit. Other embodiments are disclosed herein.

    摘要翻译： 在一些实施例中，提供了包括动态电路和体偏置电路的电路。 动态电路具有保持晶体管。 体偏置电路耦合到保持器晶体管，并且被配置为根据与动态电路相关联的泄漏来对保持器晶体管进行偏置。 本文公开了其它实施例。

    Fast static receiver with input transition dependent inversion threshold
    83.
    发明授权
    Fast static receiver with input transition dependent inversion threshold 失效
    具有输入转换相关反转阈值的快速静态接收器

    公开(公告)号：US07002389B2

    公开(公告)日：2006-02-21

    申请号：US10732791

    申请日：2003-12-09

    申请人： Atila Alvandpour ,  Ram Krishnamurthy

    发明人： Atila Alvandpour ,  Ram Krishnamurthy

    IPC分类号： H03K3/12

    CPC分类号： H03K17/164

    摘要： A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.

    摘要翻译： 具有经历高到低转换的接收信号的第一反相阈值的静态接收机，以及经历低到高转换的接收信号的第二反相阈值，其中第一反转阈值大于第二反转阈值。 一个实施例包括静态接收器，pFET和nFET，其中当在接收器的输入端口处接收到高电平到低电平的转换时，pFET耦合到输入端口，以便有助于提高反转阈值， 并且当在输入端口处接收到低电平到高电平的转换时，nFET耦合到输入端口，以便有助于降低反转阈值。 描述和要求保护其他实施例。

    Differential current sense amplifier
    85.
    发明授权
    Differential current sense amplifier 有权
    差分电流检测放大器

    公开(公告)号：US06847569B2

    公开(公告)日：2005-01-25

    申请号：US10330557

    申请日：2002-12-30

    申请人： Manoj K. Sinha ,  Ram Krishnamurthy ,  Atila Alvandpour

    发明人： Manoj K. Sinha ,  Ram Krishnamurthy ,  Atila Alvandpour

    IPC分类号： G11C7/06 ,  G11C7/02

    CPC分类号： G11C7/062 ,  G11C2207/063

    摘要： A high-performance, low energy amplifier circuit for the detection and amplification of a voltage differential includes a current conveyor and a sense amplifier. The current conveyor includes a pair of cross-linked transistors and a pair of pass transistors. The sense amplifier includes four transistors forming a cross-linked current sense amplifier. The current sense amplifier detects a current differential between complementary bit lines, develops a differential voltage based on the current differential, amplifies the differential voltage and outputs the amplified differential voltage.

    摘要翻译： 用于检测和放大电压差的高性能低能量放大器电路包括电流传输器和读出放大器。 当前的输送机包括一对交联晶体管和一对通过晶体管。 读出放大器包括形成交叉电流检测放大器的四个晶体管。 电流检测放大器检测互补位线之间的电流差，基于电流差异产生差分电压，放大差分电压并输出放大的差分电压。

    Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation
    86.
    发明授权
    Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation 失效
    多电源电压拉链CMOS逻辑系列具有低有源漏电功耗

    公开(公告)号：US06693461B2

    公开(公告)日：2004-02-17

    申请号：US10027292

    申请日：2001-12-20

    申请人： Steven K. Hsu ,  Ram Krishnamurthy

    发明人： Steven K. Hsu ,  Ram Krishnamurthy

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： An embodiment zipper circuit achieves reduced leakage current by utilizing four voltages so that FETs in the p-logic blocks and n-logic blocks are reversed biased during a pre-charge phase. The FETs in a logic block are also reversed biased during an evaluation phase if the input voltages to the logic block are such that the logic block is not driven ON during the evaluation phase.

    摘要翻译： 实施例拉链电路通过利用四个电压来实现减小的漏电流，使得在预充电阶段期间p逻辑块和n逻辑块中的FET被反向偏置。 如果逻辑块的输入电压使得在评估阶段期间逻辑块不被驱动为ON，则逻辑块中的FET在评估阶段也被反向偏置。

    Merging calendar entries
    88.
    发明授权
    Merging calendar entries 失效
    合并日历条目

    公开(公告)号：US08407075B2

    公开(公告)日：2013-03-26

    申请号：US12823417

    申请日：2010-06-25

    申请人： John M. Lance ,  David B. Cohen ,  Bruce A. Kahn ,  Gregory R. Klouda ,  Ram Krishnamurthy ,  Deborah E. Maurer ,  Frank A. Pavelski ,  Michelle Stoner

    发明人： John M. Lance ,  David B. Cohen ,  Bruce A. Kahn ,  Gregory R. Klouda ,  Ram Krishnamurthy ,  Deborah E. Maurer ,  Frank A. Pavelski ,  Michelle Stoner

    IPC分类号： G06Q10/00

    CPC分类号： G06F3/0482 ,  G06Q10/109

    摘要： A method, operable on a processing device, for merging calendar entries may include receiving a plurality of calendar entries each associated with entry identification data. The method may also include comparing by the processing device at least a portion of the entry identification data associated with each of the calendar entries. The method may additionally include merging, by the processing device, the calendar entries based at least in part on comparing of at least the portion of the entry identification data associated with each of the at least two calendar entries. The method may further include comparing at least one time attribute associated with each of the calendar entries and comparing at least one textual attribute associated with each of the calendar entries and basing merging the calendar entries additionally on comparing the time attributes and the textual attributes.

    摘要翻译： 可在处理装置上操作用于合并日历条目的方法可以包括接收与条目标识数据相关联的多个日历条目。 该方法还可以包括通过处理设备比较与每个日历条目相关联的条目标识数据的至少一部分。 该方法可以另外包括至少部分地基于与至少两个日历条目中的每一个相关联的条目标识数据的至少一部分的比较来由处理设备合并日历条目。 该方法还可以包括比较与每个日历条目相关联的至少一个时间属性，并比较与每个日历条目相关联的至少一个文本属性，并且在比较时间属性和文本属性的基础上逐步合并日历条目。

    APPARATUS AND METHOD FOR SKEIN HASHING
    89.
    发明申请
    APPARATUS AND METHOD FOR SKEIN HASHING 有权
    装置和方法进行滑雪

    公开(公告)号：US20120328097A1

    公开(公告)日：2012-12-27

    申请号：US13165269

    申请日：2011-06-21

    申请人： Farhana Sheikh ,  Jesse Walker ,  Sanu K. Mathew ,  Ram Krishnamurthy

    发明人： Farhana Sheikh ,  Jesse Walker ,  Sanu K. Mathew ,  Ram Krishnamurthy

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0861 ,  H04L9/0618 ,  H04L9/0625 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/0816 ,  H04L2209/125 ,  H04L2209/24 ,  H04N1/32277

    摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.

    摘要翻译： 这里描述了用于Skein散列的装置和方法。 该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。