公开(公告)号：US06570367B2

公开(公告)日：2003-05-27

申请号：US10090278

申请日：2002-03-04

Applicant: Rainer Bartenschlager ,  Martin Brox ,  Albert Graf V. Keyserlingk

Inventor： Rainer Bartenschlager ,  Martin Brox ,  Albert Graf V. Keyserlingk

IPC: G05F159

CPC classification number: G05F1/465

Abstract: A voltage generator for producing an internal supply voltage has a standby voltage generator and a voltage generator for normal operation that are controlled in common by a reference voltage. In addition, a comparator stage is provided whose switching threshold is set lower than the reference voltage by using a voltage divider that is connected to the reference voltage. The additional comparator stage thus activates the voltage generator for normal operation when the internally produced voltage falls below its switching threshold so that the internal supply voltage is stabilized.

公开(公告)号：US06414531B2

公开(公告)日：2002-07-02

申请号：US09780324

申请日：2001-02-09

Applicant: Martin Brox

Inventor： Martin Brox

IPC: H03H1126

CPC classification number: H03K19/00323

Abstract: In order to provide a more flexible adjustment of signal delay times in a circuit configuration containing a line device and a number of electronic components accessing it, it is proposed to add additional capacitances, which can be varied in a controllable manner. In addition, the capacitances are to formed in a region of the existing components.

Abstract translation: 为了在包含线路器件和多个电子部件的电路配置中提供对信号延迟时间的更灵活的调整，可以增加额外的电容，其可以以可控的方式变化。 此外，电容将形成在现有部件的区域中。

公开(公告)号：US6016281A

公开(公告)日：2000-01-18

申请号：US992378

申请日：1997-12-17

Applicant: Martin Brox

Inventor： Martin Brox

IPC: G11C11/401 ,  G11C8/08 ,  G11C11/408 ,  G11C29/04 ,  H01L27/108 ,  G11C8/00

CPC classification number: G11C11/4085 ,  G11C8/08 ,  H01L27/10897

Abstract: In a memory array, decoding circuitry for selectively applying a turn-off voltage to selected word lines of the memory array for turning off conduction in the main conduction paths of the transistors whose gate electrodes are connected to the selected word lines and for selectively applying an increased turn-off voltage to selected word lines. The application of different values of turn-off voltage may be used to test the susceptibility of the memory array to gate induced drain leakage (GIDL) and to determine an optimum range of turn-off voltages to be applied to the word lines for operation with reduced leakage.

Abstract translation: 在存储器阵列中，解码电路用于选择性地向存储器阵列的选定字线施加截止电压，以关闭其栅电极连接到选定字线的晶体管的主导通路径中的导通，并选择性地施加 提高关断电压到所选择的字线。 可以使用不同的关断电压值来测试存储器阵列对栅极感应漏极泄漏（GIDL）的敏感性，并且确定要施加到字线的关断电压的最佳范围以用于操作， 减少泄漏。