公开(公告)号：US07564735B2

公开(公告)日：2009-07-21

申请号：US11481157

申请日：2006-07-05

Applicant: Martin Brox ,  Thomas Hein

Inventor： Martin Brox ,  Thomas Hein

IPC: G11C7/00

CPC classification number: G11C29/26 ,  G11C11/4087 ,  G11C29/1201 ,  G11C29/46

Abstract: A memory device, in particular to a DRAM, and a system comprising a memory device is disclosed. Further, the invention relates to a method for operating a memory device. According to an embodiment of the invention, a memory device is provided, including: a first chip select pin, and a second chip select pin. Further, a method for operating a memory device is provided, the memory device including a first chip select pin, and a second chip select pin, the method including: applying a chip select signal to the first or the second chip select pin.

Abstract translation: 公开了一种存储器件，特别是DRAM，以及包括存储器件的系统。 此外，本发明涉及一种用于操作存储器件的方法。 根据本发明的一个实施例，提供了一种存储器件，包括：第一芯片选择引脚和第二芯片选择引脚。 此外，提供了一种用于操作存储器件的方法，所述存储器件包括第一芯片选择引脚和第二芯片选择引脚，所述方法包括：将片选信号施加到第一芯片选择引脚或第二芯片选择引脚。

公开(公告)号：US07515456B2

公开(公告)日：2009-04-07

申请号：US11530858

申请日：2006-09-11

Applicant: Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

Inventor： Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

IPC: G11C11/00

CPC classification number: G11C7/16 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4085 ,  G11C11/4096

Abstract: A memory circuit comprises a D/A converter connected with an input/output circuit and with a writing circuit, wherein the D/A converter converts a digital data with at least two digital bits received from the input/output circuit to one analog value and forwards the analog value to the writing circuit, wherein the digital data is at least a part of a floating point number, wherein the writing circuit writes the analog value in at least one selected memory cell, and an A/D converter connected with a reading circuit and with the input/output circuit, wherein the reading circuit reads an analog value from a selected memory cell and forwards the analog value to the A/D converter, wherein the A/D converter converts the analog value to digital data, and wherein the A/D converter forwards the digital data to the input/output circuit. Furthermore, a method is provided for reading data from at least one memory cell of a memory, wherein an analog value is read from the memory cell and the analog value is corrected according to a correction factor representing a storage time the analog value was stored and wherein the corrected analog value is converted to digital data.

Abstract translation: 存储电路包括与输入/输出电路和写入电路连接的D / A转换器，其中D / A转换器将具有从输入/输出电路接收的至少两个数字位的数字数据转换成一个模拟值， 将模拟值转发到写入电路，其中数字数据是浮点数的至少一部分，其中写入电路将模拟值写入至少一个选择的存储单元，以及与读取器连接的A / D转换器 电路和输入/输出电路，其中读取电路从所选择的存储器单元读取模拟值并将模拟值转发到A / D转换器，其中A / D转换器将模拟值转换为数字数据，其中 A / D转换器将数字数据转发到输入/输出电路。 此外，提供一种用于从存储器的至少一个存储单元读取数据的方法，其中从存储器单元读取模拟值，并且根据表示存储模拟值的存储时间的校正因子来校正模拟值，以及 其中所述经修正的模拟值被转换为数字数据。

公开(公告)号：US20090045856A1

公开(公告)日：2009-02-19

申请号：US11838634

申请日：2007-08-14

Applicant: Wolfgang Spirkl ,  Martin Brox ,  Holger Steffens

Inventor： Wolfgang Spirkl ,  Martin Brox ,  Holger Steffens

IPC: H03L7/06

CPC classification number: H03L7/0814

Abstract: One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator. The phase interpolator is activated when the incoming clock signal and the inverted delayed clock signal are substantially in phase and adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1.

Abstract translation: 一个方面涉及一种时钟信号同步装置，特别涉及具有校正静态占空比偏移和滤波时钟抖动能力的延迟锁定环（DLL）。 一个方面涉及具有校正静态占空比偏移和滤波时钟抖动能力的时钟信号同步方法。 根据一个方面，提供了一种时钟信号同步装置，其包括具有可变延迟时间并延迟输入时钟信号或由其产生的信号的延迟电路以输出延迟的时钟信号。 还包括用于反相延迟时钟信号以输出反相延迟时钟信号的否定器。 还包括延迟控制电路，用于控制延迟电路以调整输入时钟信号和反相延迟时钟信号之间的相位关系以及相位插值器。 当输入时钟信号和反相延迟时钟信号基本上同相时，相位内插器被激活，并将输入时钟信号乘以基本上为（1-p）的因子到反相延迟的时钟信号乘以基本上为p的因子 将复合信号输出到延迟电路，p是大于或等于0且小于或等于1的实数。

公开(公告)号：US07420867B2

公开(公告)日：2008-09-02

申请号：US10569859

申请日：2004-07-09

Applicant: Martin Brox

Inventor： Martin Brox

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096

Abstract: A method for operating a semiconductor memory device is disclosed. In one embodiment, the method includes activating a first memory cell sub-array or memory cells of the first memory cell sub-array that are contained in a first set of memory cells, in particular of memory cells positioned in one and the same row or column of the first memory cell sub-array, if one or a plurality of memory cells contained in the first memory cell sub-array or in the first set of memory cells is/are to be accessed. The corresponding memory cell or memory cells are accessed; including leaving the first memory cell sub-array or the memory cells of the first memory cell sub-array that are contained in the first set of memory cells in the activated state if one or a plurality of further memory cells is/are to be accessed which are contained in a second memory cell sub-array of the same memory cell array that comprises the first memory cell sub-array.

Abstract translation: 公开了一种用于操作半导体存储器件的方法。 在一个实施例中，该方法包括激活包含在第一组存储器单元中的第一存储单元子阵列的第一存储单元子阵列或存储单元，特别是定位在同一行或 如果第一存储单元子阵列中包含的一个或多个存储单元或第一组存储器单元中的一个或多个存储器单元将被访问，则第一存储单元子阵列的列将被访问。 访问相应的存储单元或存储单元; 包括如果要访问一个或多个另外的存储器单元，则将处于激活状态的包含在第一组存储器单元中的第一存储单元子阵列或第一存储单元子阵列的存储单元留下 其包含在包括第一存储单元子阵列的相同存储单元阵列的第二存储单元子阵列中。

公开(公告)号：US20080117223A1

公开(公告)日：2008-05-22

申请号：US11602716

申请日：2006-11-21

Applicant: Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

Inventor： Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

IPC: G06T1/60

CPC classification number: G06F3/14 ,  G09G5/363 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2360/06 ,  G09G2360/18

Abstract: A display having a screen, and memory for storing picture data is disclosed. In one embodiment, the screen includes a plurality of pixels, the pixels in a first mode of the display being controlled by the picture data stored in the memory, and in a second mode of the display being controlled by picture data received from an external processing unit.

Abstract translation: 公开了一种具有屏幕的显示器和用于存储图像数据的存储器。 在一个实施例中，屏幕包括多个像素，显示器的第一模式中的像素由存储在存储器中的图像数据控制，并且显示器的第二模式由从外部处理接收的图像数据控制 单元。

公开(公告)号：US20060103446A1

公开(公告)日：2006-05-18

申请号：US11260506

申请日：2005-10-27

Applicant: Martin Brox ,  Maksim Kuzmenka

Inventor： Martin Brox ,  Maksim Kuzmenka

IPC: H03L5/00

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: A circuit for coupling a logic signal from a circuit input to a circuit output includes a parallel connection of a first circuit branch and a second circuit branch, wherein an inverter in the first branch powered as last inverter in this branch via first supply terminals, via which a first supply potential and a second supply potential are supplied, and an inverter in the second branch powered as first inverter in this branch via second supply voltage terminals, via which a second supply potential and a second reference potential are supplied, are adapted to receive the same logic value of the logic signal, wherein outputs of the two circuit branches are connected to each other and coupled to the circuit output. In such a circuit, propagation time differences of rising and falling edges, which may develop by fluctuation of various supply potentials, may be minimized. Thus, a transition from an internal supply potential to an external supply potential may take place, without noticeably degrading the signal timing.

Abstract translation: 用于将逻辑信号从电路输入耦合到电路输出的电路包括第一电路分支和第二电路分支的并联连接，其中第一分支中的逆变器通过第一供电端经由该分支中的最后一个反相器供电，经由 提供第一供电电位和第二供电电位的第二分支中的第二分支中的逆变器，通过第二供电电压和第二参考电位经由第二供电电压端子供电的第一逆变器中的逆变器适于 接收逻辑信号相同的逻辑值，其中两个电路分支的输出彼此连接并耦合到电路输出。 在这种电路中，由于各种电源电位的波动可能产生的上升沿和下降沿的传播时间差可能被最小化。 因此，可能发生从内部电源电位到外部电源电位的转变，而不会明显降低信号时序。

公开(公告)号：US20060087896A1

公开(公告)日：2006-04-27

申请号：US10974019

申请日：2004-10-27

Applicant: Martin Brox ,  Russell Houghton ,  Helmut Schneider ,  Sabine Kieser

Inventor： Martin Brox ,  Russell Houghton ,  Helmut Schneider ,  Sabine Kieser

IPC: G11C16/04

CPC classification number: G11C11/4076 ,  G11C7/22 ,  G11C11/4096 ,  G11C2207/002

Abstract: The invention relates to semiconductor memories and in particular to DRAMs. A semiconductor memory is provided comprising at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal, further comprising a tri-state driver device for driving the control signal. Further, a method for operating a memory is provided, the memory comprising a memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal, the method comprising the steps: driving the control signal at a first voltage level when a read operation is to be performed; and driving the control signal at a second voltage level different from the first voltage level when a write operation is to be performed. Advantageously, the first voltage level used for the read operation is lower than the second voltage level used for the write operation.

Abstract translation: 本发明涉及半导体存储器，特别涉及DRAM。 提供一种半导体存储器，其包括至少一个适于存储数据值的存储单元，并且适于通过由控制信号控制的开关装置连接到数据线，还包括用于驱动控制信号的三态驱动器装置 。 此外，提供了一种用于操作存储器的方法，所述存储器包括适于存储数据值的存储单元，并且适于通过由控制信号控制的开关装置连接到数据线，所述方法包括以下步骤：驱动 当要执行读取操作时处于第一电压电平的控制信号; 以及当要执行写入操作时，以与所述第一电压电平不同的第二电压电平驱动所述控制信号。 有利地，用于读取操作的第一电压电平低于用于写入操作的第二电压电平。

公开(公告)号：US06996026B2

公开(公告)日：2006-02-07

申请号：US10834383

申请日：2004-04-29

Applicant: Martin Brox ,  Alessandro Minzoni

Inventor： Martin Brox ,  Alessandro Minzoni

IPC: G11C8/00

CPC classification number: G11C7/222 ,  G11C7/22 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/087

Abstract: A clock signal synchronizing device includes a first delay unit with variable delay time connected to an input circuit with a first delay time which receives a first clock signal and outputs a second clock signal. A second delay unit has a fixed delay time portion corresponding to the first delay time, and an additional variable delay time portion. A first phase comparison unit has a first input connected to the output of the input circuit, and a second input connected to the output of the second delay unit. The output signal controls the delay time of the first delay unit. A copy of the input circuit has an input connected to the output of the first delay unit. A second phase comparison unit has an input connected to the output of the copy, and an output signal controls the variable delay time portion of the second delay unit.

Abstract translation: 时钟信号同步装置包括具有连续到输入电路的可变延迟时间的第一延迟单元，其具有接收第一时钟信号并输出​​第二时钟信号的第一延迟时间。 第二延迟单元具有对应于第一延迟时间的固定延迟时间部分和附加可变延迟时间部分。 第一相位比较单元具有连接到输入电路的输出的第一输入和连接到第二延迟单元的输出的第二输入。 输出信号控制第一延迟单元的延迟时间。 输入电路的副本具有连接到第一延迟单元的输出的输入。 第二相位比较单元具有连接到副本的输出的输入，并且输出信号控制第二延迟单元的可变延迟时间部分。

公开(公告)号：US06956304B2

公开(公告)日：2005-10-18

申请号：US10389782

申请日：2003-03-17

Applicant: Martin Brox

Inventor： Martin Brox

IPC: H02J1/10 ,  H02J1/00

CPC classification number: H02J1/10 ,  Y10T307/505 ,  Y10T307/735

Abstract: Integrated circuit, which is supplied externally by a supply voltage, having at least one useful circuit and a power supply for the at least one useful circuit which comprises a plurality of power supply units, in which case the power supply comprises a control unit for comparing the supply voltage with a predetermined desired value and for switching one or a plurality of the switchable power supply units on or off in a manner dependent on the comparison result.

Abstract translation: 由电源电压外部提供的集成电路具有至少一个有用电路和用于至少一个有用电路的电源，该有用电路包括多个电源单元，在这种情况下，电源包括用于比较的控制单元 电源电压具有预定的期望值，并且以取决于比较结果的方式开启或关闭一个或多个可切换电源单元。

公开(公告)号：US06560134B2

公开(公告)日：2003-05-06

申请号：US10014776

申请日：2001-11-07

Applicant: Martin Brox ,  Karl-Peter Pfefferl ,  Helmut Schneider ,  Robert Kaiser ,  Dominique Savignac

Inventor： Martin Brox ,  Karl-Peter Pfefferl ,  Helmut Schneider ,  Robert Kaiser ,  Dominique Savignac

IPC: G11C502

CPC classification number: G11C5/025 ,  H01L23/50 ,  H01L24/02 ,  H01L27/10805 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082

Abstract: A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.