公开(公告)号：US6104275A

公开(公告)日：2000-08-15

申请号：US147845

申请日：1999-03-18

申请人： Atsushi Maeda

发明人： Atsushi Maeda

IPC分类号： G01R33/09 ,  G11B5/39 ,  H01F10/32 ,  H01L43/08 ,  H01L43/06

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G01R33/093 ,  G11B5/3903 ,  H01F10/324 ,  H01L43/08 ,  G11B2005/3996

摘要： A magnetoresistive element is obtained which can exhibit a larger MR change than conventional.The magnetoresistive element is characterized as comprising a multilayer film 3 having a multilayer structure in which a nonmagnetic conductive layer 5 is interposed between a pair of ferromagnetic layer 4, 6, a pair of electrodes 7, 8 which produces a detection current flow through the multilayer film 3, and filter layers 1, 2 comprised of ferromagnetic material and disposed between at least one of the pair of ferromagnetic layers and the electrodes 7, 8 for delivering spin-polarized electrons to the ferromagnetic layers 4, 6, and characterized that a traveling distance of electrons in the ferromagnetic layers 4, 6 is maintained shorter than a spin diffusion length.

摘要翻译： PCT No.PCT / JP97 / 03270 Sec。 371 1999年3月18日 102（e）1999年3月18日PCT 1997年9月16日PCT公布。 公开号WO98 / 12758 日期1998年3月26日获得可以表现出比传统的更大的MR变化的磁阻元件。 磁阻元件的特征在于包括具有多层结构的多层膜3，其中非磁性导电层5插入在一对铁磁层4,6之间，产生检测电流流过多层膜的电极7,8 膜3和由铁磁材料构成的滤光层1,2，并且设置在一对铁磁层中的至少一个和电极7,8之间，用于将自旋极化电子传递到铁磁层4,6，并且其特征在于，行进 铁磁层4,6中电子的距离保持短于自旋扩散长度。

公开(公告)号：US6064099A

公开(公告)日：2000-05-16

申请号：US285044

申请日：1999-04-01

申请人： Keiichi Yamada ,  Atsushi Maeda ,  Kenji Yoshiyama ,  Keiichi Higashitani

发明人： Keiichi Yamada ,  Atsushi Maeda ,  Kenji Yoshiyama ,  Keiichi Higashitani

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/74 ,  H01L23/485 ,  H01L29/417 ,  H01L29/41

CPC分类号： H01L29/66636 ,  H01L21/743 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41766 ,  H01L2924/0002

摘要： There is described a semiconductor device intended to increase a degree of integration of transistor without impairing a desired element characteristic. An n-type source region and an n-type drain region are formed in a p-well which acts as a substrate region of an NMOS transistor. Further, there are formed a first contact plug to be electrically connected to the n-type source region and a second contact plug to be electrically connected to the n-type drain region. The n-type source region is provided so as to become short-circuited with the p-well. The n-type drain region is provided so as not to become short-circuited with the p-well. The n-type source region is formed so as to become smaller than the n-type drain region.

摘要翻译： 描述了一种旨在增加晶体管集成度而不损害所需元件特性的半导体器件。 在作为NMOS晶体管的基板区域的p阱中形成n型源极区域和n型漏极区域。 此外，形成电连接到n型源极区域的第一接触插塞和与n型漏极区域电连接的第二接触插塞。 n型源极区域被设置为与p阱短路。 设置n型漏极区以不与p阱短路。 n型源极区域形成为小于n型漏极区域。