公开(公告)号：US08885720B2

公开(公告)日：2014-11-11

申请号：US13966538

申请日：2013-08-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Satoshi Kondo ,  Shinya Kadono ,  Makoto Hagai ,  Kiyofumi Abe

IPC: H04N7/36 ,  H04N19/593 ,  H04N19/61 ,  H04N19/56 ,  H04N19/577 ,  H04N19/51 ,  H04N19/50 ,  H04N19/583

CPC classification number: H04N19/52 ,  H04N19/105 ,  H04N19/137 ,  H04N19/139 ,  H04N19/172 ,  H04N19/176 ,  H04N19/184 ,  H04N19/50 ,  H04N19/51 ,  H04N19/513 ,  H04N19/517 ,  H04N19/521 ,  H04N19/533 ,  H04N19/537 ,  H04N19/56 ,  H04N19/577 ,  H04N19/593 ,  H04N19/61

Abstract: A motion vector coding unit executes processing including a neighboring block specification step of specifying a neighboring block which is located in the neighborhood of a current block; a judgment step of judging whether or not the neighboring block has been coded using a motion vector of another block; a prediction step of deriving a predictive motion vector of the current block using a motion vector calculated from the motion vector of the other block as a motion vector of the neighboring block; and a coding step of coding the motion vector of the current block using the predictive motion vector.

公开(公告)号：US12294707B2

公开(公告)日：2025-05-06

申请号：US18587635

申请日：2024-02-26

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/13 ,  H04N19/169 ,  H04N19/176 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.

公开(公告)号：US12294696B2

公开(公告)日：2025-05-06

申请号：US18529380

申请日：2023-12-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Che Wei Kuo ,  Hai Wei Sun ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/14 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: determines whether a size of a current block, which is a unit for which a vector candidate list including vector candidates is generated, is less than or equal to a threshold; when the size of the current block is less than or equal to the threshold, generates the vector candidate list by registering a history-based motion vector predictor (HMVP) vector candidate in the vector candidate list from an HMVP table without performing a first pruning process; when the size of the current block is greater than the threshold, generates the vector candidate list by performing the first pruning process and registering the HMVP vector candidate in the vector candidate list from the HMVP table; and encodes the current block using the vector candidate list.

公开(公告)号：US12289462B2

公开(公告)日：2025-04-29

申请号：US17642448

申请日：2020-12-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Han Boon Teo ,  Hai Wei Sun ,  Jing Ya Li ,  Che Wei Kuo ,  Chong Soon Lim ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/00 ,  H04N19/105 ,  H04N19/176 ,  H04N19/46 ,  H04N19/80

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry writes, into a bitstream, a first flag indicating whether or not to enable a first process of applying a filter to a first image to generate a second image, holding the second image as a reference image, and displaying the second image. When the first process is not enabled, circuitry writes, into the bitstream, one or more parameters for controlling a second process of applying the filter to the first image to generate the second image, holding the first image as a reference image, and displaying the second image.

公开(公告)号：US12273522B2

公开(公告)日：2025-04-08

申请号：US18111106

申请日：2023-02-17

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Jing Ya Li ,  Han Boon Teo ,  Ru Ling Liao ,  Che Wei Kuo ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe

IPC: H04N19/13 ,  H04N19/176

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, determines whether a first block is available and whether a second block is available, the first block and the second block being defined relative to a current block to be processed; selects a context model based on whether the first block is available, whether the second block is available, which of inter prediction and intra prediction is to be applied to the first block, and which of inter prediction and intra prediction is to be applied to the second block; and encodes, using the context model selected, a parameter indicating which of intra prediction and inter prediction is to be applied to the current block.

公开(公告)号：US12267499B2

公开(公告)日：2025-04-01

申请号：US18403086

申请日：2024-01-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70 ,  H04N19/91

Abstract: A decoder includes circuitry and memory. In both of a first type of residual decoding where an inverse orthogonal transform is applied and a second type of residual decoding where the inverse orthogonal transform is skipped, wherein when a restriction on a number of CABAC processes allows CABAC decoding of a set of coefficient information flags, the circuitry: decodes the coefficient information flags by CABAC; and otherwise, the circuitry: skips the CABAC decoding of the coefficient information flags; and the circuitry decodes a remainder value of the coefficient with Golomb-Rice decoding when the coefficient information flags are decoded; and otherwise the circuitry decodes a value of the coefficient with the Golomb-Rice decoding, wherein in the second type of residual decoding, the circuitry decodes absolute value flags each relating to an absolute value of the coefficient after decoding the coefficient information flags and before decoding the remainder value of the coefficient.

公开(公告)号：US12262049B2

公开(公告)日：2025-03-25

申请号：US18545682

申请日：2023-12-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N11/02 ,  H04N19/119 ,  H04N19/176 ,  H04N19/52

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.

公开(公告)号：US12262004B2

公开(公告)日：2025-03-25

申请号：US17582950

申请日：2022-01-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Che-Wei Kuo ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Hai Wei Sun ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/132 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/82

Abstract: An encoder includes circuitry which generates a first coefficient value by applying a CCALF process to a first reconstructed image sample of a luma component; generates a second coefficient value by applying an ALF process to a second reconstructed image sample of a chroma component; generates a third coefficient value by adding the first coefficient value to the second coefficient value; and encodes a third reconstructed image sample of the chroma component using the third coefficient value. The circuitry writes a first parameter into a sequence parameter set; writes a second parameter into a parameter set of a picture in response to a value of the first parameter being 1; writes a third parameter into a slice header in response to the value of the first parameter being 1; and writes a fourth parameter into a coding tree unit in response to a value of the third parameter being 1.

公开(公告)号：US20250047899A1

公开(公告)日：2025-02-06

申请号：US18921409

申请日：2024-10-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: stores MV information and correction processing information into a FIFO buffer for an HMVP mode in association, the MV information being derived for a processed block and correction processing information being related to correction processing of a prediction image of the processed block; registers, in a prediction candidate list for a merge mode, one or more prediction candidates each being a combination of MV information and correction processing information, the prediction candidates including a prediction candidate which is a combination of the motion vector information and the correction processing information stored in the FIFO buffer; and selects a prediction candidate from the prediction candidate list when a current block is to be processed in the merge mode, and performs correction processing of a prediction image of the current block, based on the correction processing information.

公开(公告)号：US12219155B2

公开(公告)日：2025-02-04

申请号：US18591350

申请日：2024-02-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/159 ,  H04N19/119 ,  H04N19/139 ,  H04N19/513

Abstract: An encoder encodes a video, and includes: circuitry; and memory coupled to the circuitry. Using the memory, the circuitry: obtains at least two items of prediction information for a first partition included in the video; derives at least one template from neighboring samples which neighbor the first partition; calculates at least two costs, using the at least one template and the at least two items of prediction information; using the at least two costs, (i) determines at least one splitting direction for the first partition or (ii) assigns one of the at least two items of prediction information to a second partition split from the first partition according to the splitting direction, and another thereof to a third partition split from the first partition according to the splitting direction; and encodes the first partition according to the splitting direction and the at least two items of prediction information.