公开(公告)号：USRE34158E

公开(公告)日：1993-01-12

申请号：US744514

申请日：1991-08-13

申请人： Atsuo Watanabe ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma ,  Ryuichi Saito

发明人： Atsuo Watanabe ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma ,  Ryuichi Saito

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L27/0928 ,  H01L21/76224 ,  H01L21/763 ,  H01L21/823892 ,  H01L27/0623

摘要： A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the wall from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.

公开(公告)号：US4916500A

公开(公告)日：1990-04-10

申请号：US78987

申请日：1987-07-29

申请人： Yoshiaki Yazawa ,  Atsuo Watanabe ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano

发明人： Yoshiaki Yazawa ,  Atsuo Watanabe ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/808

CPC分类号： H01L29/78696 ,  H01L29/105 ,  H01L29/78 ,  H01L29/7838 ,  H01L29/808

摘要： The present invention relates to a semiconductor device comprising a semiconductor substrate of a first conductivity type or an insulator, a source comprising an impurity layer of a second conductivity type disposed on said semiconductor substrate or said insulator, a drain comprising an impurity layer of the second conductivity type disposed on said semiconductor substrate or said insulator, an impurity layer of the first conductivity type formed between said source and said drain, a gate formed on said impurity layer of the first conductivity type via an insulation film, and an impurity layer of the second conductivity type having an impurity concentration lower than that of said source and said drain, said impurity layer of the second conductivity type being disposed between said source, said drain and said impurity layer of the first conductivity type, and said semiconductor substrate of the first conductivity type or said insulator.

摘要翻译： 本发明涉及一种包括第一导电类型或绝缘体的半导体衬底的半导体器件，包括设置在所述半导体衬底或所述绝缘体上的第二导电类型的杂质层的源极，包括第二导电类型或绝缘体的杂质层的漏极 设置在所述半导体衬底或所述绝缘体上的导电类型，形成在所述源极和所述漏极之间的第一导电类型的杂质层，经由绝缘膜形成在所述第一导电类型的所述杂质层上的栅极和 第二导电类型的杂质浓度低于所述源极和漏极的第二导电类型，所述第二导电类型的所述杂质层设置在所述源极，所述漏极和所述第一导电类型的所述杂质层之间，所述第一导电类型的所述半导体衬底 导电类型或所述绝缘体。

公开(公告)号：US4862240A

公开(公告)日：1989-08-29

申请号：US85260

申请日：1987-08-12

申请人： Atsuo Watanabe ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma ,  Ryuichi Saito

发明人： Atsuo Watanabe ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma ,  Ryuichi Saito

IPC分类号： H01L29/78 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L21/76224 ,  H01L21/74 ,  H01L21/76205 ,  H01L21/763 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0623

摘要： A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the well from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.

摘要翻译： 一种单片互补半导体器件，包括由从表面延伸到衬底区域的电介质隔离区隔开的n型和p型阱区。 阱区域包括高度掺杂的掩埋区域，其位于阱区域的底部并且将阱中的有源区域与衬底区域分离。 隔离区域比掩埋区域深。 通过掩埋区域和深介电隔离区域的组合增强了井对阱隔离。 包装密度和高速运转也可以提高。

公开(公告)号：US4626888A

公开(公告)日：1986-12-02

申请号：US550586

申请日：1983-11-10

申请人： Takahiro Nagano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Akira Horie

发明人： Takahiro Nagano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Akira Horie

IPC分类号： H01L29/423 ,  H01L29/74 ,  H01L29/744 ,  H01L23/48

CPC分类号： H01L29/42308 ,  H01L29/74 ,  H01L29/744

摘要： In accordance with the present invention, a plurality of strip-shaped emitter layers on the cathode side are radially arranged on one main surface of the semiconductor substrate while forming a plurality of rings. A gate electrode is in ohmic contact with a part of a base layer which surrounds and is adjacent to each of said emitter layers on the cathode side. Between rings formed by said emitter layers on the cathode side, a ring-shaped gate collecting electrode is provided to be connected to said gate electrode. The gate collecting electrode is provided at a position to balance the potential differences produced by gate currents respectively corresponding to inside and outside of said gate collecting electrode.

摘要翻译： 根据本发明，阴极侧的多个条状发射极层径向地布置在半导体衬底的一个主表面上，同时形成多个环。 栅电极与基极层的一部分欧姆接触，该基极层围绕并邻近阴极侧的每个发射极层。 在由阴极侧上的发射极层形成的环之间，设置有环形栅极集电极，以连接到所述栅电极。 栅极集电极设置在平衡由分别对应于所述栅极集电极的内部和外部的栅极电流产生的电位差的位置。

公开(公告)号：US4443810A

公开(公告)日：1984-04-17

申请号：US320536

申请日：1981-11-12

申请人： Tsutomu Yatsuo ,  Takahiro Nagano

发明人： Tsutomu Yatsuo ,  Takahiro Nagano

IPC分类号： H01L29/74 ,  H01L29/744

CPC分类号： H01L29/744

摘要： A gate turn-off thyristor is disclosed which includes a main thyristor having a shorted emitter structure on the anode side thereof and an auxiliary thyristor having a shorted emitter structure on the cathode side thereof and wherein the cathode of the auxiliary thyristor is connected to the gate of the main thyristor to on-off control a large current by a small gate signal.

摘要翻译： 公开了一种栅极截止晶闸管，其包括在其阳极侧具有短路发射极结构的主晶闸管和在其阴极侧具有短路发射极结构的辅助晶闸管，并且其中辅助晶闸管的阴极连接到栅极 的主晶闸管开关通过小门信号控制大电流。

公开(公告)号：US3953375A

公开(公告)日：1976-04-27

申请号：US441318

申请日：1974-02-11

申请人： Takahiro Nagano ,  Michio Oue

发明人： Takahiro Nagano ,  Michio Oue

IPC分类号： H01C7/10 ,  C04B35/46 ,  C04B35/475 ,  H01C7/115 ,  H01B1/06 ,  H01C1/06

CPC分类号： H01C7/115 ,  C04B35/46 ,  C04B35/475

摘要： A sintered, non-linear voltage titanium oxide resistance element, including, as a principal component, titanium oxide, to which are added niobium oxide and bismuth oxide.

摘要翻译： 一种烧结的非线性电压氧化钛电阻元件，其包括作为主要成分的氧化钛，向其中加入氧化铌和氧化铋。

公开(公告)号：US3943547A

公开(公告)日：1976-03-09

申请号：US421265

申请日：1973-12-03

申请人： Takahiro Nagano ,  Tatsuya Kamei ,  Takuzo Ogawa

发明人： Takahiro Nagano ,  Tatsuya Kamei ,  Takuzo Ogawa

IPC分类号： H01L23/31 ,  H01L29/00 ,  H01L29/06 ,  H01L29/743

CPC分类号： H01L29/0661 ,  H01L23/3157 ,  H01L29/00 ,  H01L2924/0002

摘要： A semiconductor device comprising a semiconductor substrate including at least three layers of alternating conductivity between a pair of principal surfaces, the side surface of said semiconductor substrate being formed in pulley-shape and the depth of the valley of the pulley-shape being selected from the most appropriate numerical range related with the dielectric constant of the surrounding medium and the thickness of the semiconductor substrate.

摘要翻译： 一种半导体器件，包括半导体衬底，所述半导体衬底在一对主表面之间包括至少三个交替导电层，所述半导体衬底的侧表面形成为滑轮形状，并且所述滑轮形状的谷的深度选自 最适合的数值范围与周围介质的介电常数和半导体衬底的厚度有关。

公开(公告)号：US08835933B2

公开(公告)日：2014-09-16

申请号：US13392786

申请日：2010-08-27

申请人： Takahiro Nagano ,  Mitsuo Okamoto ,  Tsutomu Yatsuo ,  Kenji Fukuda

发明人： Takahiro Nagano ,  Mitsuo Okamoto ,  Tsutomu Yatsuo ,  Kenji Fukuda

IPC分类号： H01L29/15 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16

CPC分类号： H01L29/7834 ,  H01L29/1608 ,  H01L29/66068

摘要： A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.

摘要翻译： 在一导电型SiC半导体区域（2）中形成有源极区和漏极区（3,4）的SiC MISFET，其中形成具有预定深度的凹部（5） 夹在所述源极和漏极区之间的所述SiC半导体区域，其中所述凹部具有与所述源极和漏极区域接触的两个侧面，以及连接所述两个侧面的底面，并且其中所述凹部的所述部分（3a，4a） 与凹部的底面的两端附近相邻的源极和漏极区域比其它部分薄。

公开(公告)号：US08824782B2

公开(公告)日：2014-09-02

申请号：US13456736

申请日：2012-04-26

申请人： Hideyuki Ichihashi ,  Takahiro Nagano ,  Nobuhiro Ogawa

发明人： Hideyuki Ichihashi ,  Takahiro Nagano ,  Nobuhiro Ogawa

IPC分类号： G06K9/62

CPC分类号： G06T5/002 ,  G06T5/50 ,  G06T2207/10016 ,  G06T2207/20182 ,  G06T2207/20221

摘要： There is provided an addition ratio learning apparatus including a noise adding unit that adds noises to data of an image input as a teacher image, a motion compensating unit that sets an image where time addition noise reduction processing is executed as an NR screen and performs motion compensation with respect to the NR screen, a differential feature amount calculating unit that sets an image as an input screen and calculates a differential feature amount, a circulation history specifying unit that counts a circulation history in the time addition noise reduction processing and specifies the circulation history, an addition ratio computing unit that computes an addition ratio on the basis of pixel values, and a time adding unit that performs multiplication by a coefficient determined according to the computed addition ratio to perform weighted addition and executes the time addition noise reduction processing with respect to the input screen.

摘要翻译： 提供了一种附加比率学习装置，包括对作为教师图像输入的图像的数据添加噪声的噪声添加单元，将执行时间附加噪声降低处理的图像设置为NR屏幕并进行运动的运动补偿单元 相对于NR屏幕的补偿，将图像设置为输入画面并计算差分特征量的差分特征量计算单元，对时间附加噪声降低处理中的循环历史进行计数并指定循环的循环历史指定单元 历史，基于像素值计算相加比率的加法比计算单元，以及根据所计算的加法比率确定的系数进行乘法的时间附加单元，以执行加权相加处理，并且执行加法噪声降低处理， 尊重输入画面。

公开(公告)号：US08363970B2

公开(公告)日：2013-01-29

申请号：US12326413

申请日：2008-12-02

申请人： Yasuhiro Suto ,  Tetsujiro Kondo ,  Hisakazu Shiraki ,  Takahiro Nagano ,  Noriaki Takahashi

发明人： Yasuhiro Suto ,  Tetsujiro Kondo ,  Hisakazu Shiraki ,  Takahiro Nagano ,  Noriaki Takahashi

IPC分类号： G06K9/40

CPC分类号： G06T5/002 ,  H04N19/98

摘要： An image processing apparatus for converting a first image into a second image having higher image quality than the first image. The image processing apparatus including first pixel value extracting means for extracting plural pixel values within the first image and estimate noise amount arithmetically operating means for obtaining estimate noise amounts for the plural pixel values. The image processing apparatus also including processing coefficient generating means for generating second processing coefficients in accordance with an arithmetic operation for first processing coefficients and the estimate noise amounts, second pixel value extracting means for extracting a plurality of pixel values, and predicting means for generating a pixel value of the pixel of interest.

摘要翻译： 一种图像处理装置，用于将第一图像转换成具有比第一图像更高的图像质量的第二图像。 该图像处理装置包括：第一像素值提取装置，用于提取第一图像内的多个像素值，并估计用于获得多个像素值的估计噪声量的噪声量算术运算装置。 该图像处理装置还包括处理系数产生装置，用于根据第一处理系数和估计噪声量的算术运算产生第二处理系数，第二像素值提取装置，用于提取多个像素值;以及预测装置， 感兴趣像素的像素值。