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    METHOD FOR FORMING A MFMIS MEMORY DEVICE
    81.
    发明申请
    METHOD FOR FORMING A MFMIS MEMORY DEVICE 有权

    公开(公告)号：US20220059549A1

    公开(公告)日：2022-02-24

    申请号：US17518950

    申请日：2021-11-04

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Sheng-Chih Lai ,  Chung-Te Lin

    IPC: H01L27/1159 ,  H01L27/11592 ,  H01L27/11595 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/1158 ,  H01L27/11597

    Abstract: Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

    Integrated circuit having angled conductive feature
    83.
    发明授权
    Integrated circuit having angled conductive feature 有权

    公开(公告)号：US11024622B2

    公开(公告)日：2021-06-01

    申请号：US16722324

    申请日：2019-12-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Ting-Wei Chiang ,  Li-Chun Tien

    IPC: H01L27/02 ,  G06F30/39 ,  G06F30/392 ,  G06F30/398 ,  H01L23/528 ,  H01L27/092

    Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.

    Method of forming layout design
    87.
    发明授权
    Method of forming layout design 有权
    形成布局设计的方法

    公开(公告)号：US09336348B2

    公开(公告)日：2016-05-10

    申请号：US14484588

    申请日：2014-09-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tung-Heng Hsieh ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Min-Hsiung Chiang ,  Ting-Wei Chiang ,  Li-Chun Tien

    IPC: G06F17/50

    CPC classification number: H01L21/82345 ,  G06F17/5072 ,  H01L21/3043 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

    Abstract translation: 公开了一种形成用于制造集成电路（IC）的布局设计的方法。 该方法包括识别由布局设计的多个门结构布局图案的一个或多个段所占据的布局设计中的一个或多个区域; 以及生成与所识别的一个或多个区域重叠的一组布局模式。 多个栅极结构布局图案具有比预定光刻技术的空间分辨率小的预定间距。 布置图案集合的第一布局图案具有小于预定间距的两倍的宽度。

    MECHANISMS FOR FORMING PATTERNS
    88.
    发明申请
    MECHANISMS FOR FORMING PATTERNS 有权

    公开(公告)号：US20150147887A1

    公开(公告)日：2015-05-28

    申请号：US14090848

    申请日：2013-11-26

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ru-Gun Liu ,  Chung-Te Lin ,  Ming-Feng Shieh ,  Tsai-Sheng Gau ,  Shih-Ming Chang

    IPC: H01L21/306 ,  H01L21/308

    CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338

    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

    Integrated circuit and manufacturing method thereof
    89.
    发明授权
    Integrated circuit and manufacturing method thereof 有权

    公开(公告)号：US12279414B2

    公开(公告)日：2025-04-15

    申请号：US17844040

    申请日：2022-06-19

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Katherine H Chiang ,  Chung-Te Lin

    IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H10B20/20

    Abstract: An integrated circuit includes a substrate, a first transistor, and an interconnect structure. The first transistor is over the substrate. The interconnect structure is disposed on the substrate and includes a first dielectric layer and a memory module. The memory module includes a first memory device, a second memory device, and a third memory device. The first memory device is embedded in the first dielectric layer. The second memory device is disposed aside the first memory device and is embedded in the first dielectric layer. The first memory device, the second memory device, and the third memory device are different types of memory devices.

    Vertical fuse memory in one-time program memory cells
    90.
    发明授权
    Vertical fuse memory in one-time program memory cells 有权

    公开(公告)号：US12266408B2

    公开(公告)日：2025-04-01

    申请号：US18357278

    申请日：2023-07-24

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Sheng-Chih Lai ,  Chung-Te Lin

    IPC: G11C17/16 ,  G11C17/18 ,  H10B20/25

    Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) memory structure. The IC memory structure includes a first conductor over a substrate and a second conductor over the first conductor. The first conductor is vertically separated from the second conductor by an isolation structure. A first channel structure is arranged on a sidewall of the isolation structure. The first channel structure is vertically between the first conductor and the second conductor. A vertical gate electrode is disposed along sidewalls of the first conductor, the second conductor, and the first channel structure. The sidewall of the first channel structure faces away from the isolation structure.

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