公开(公告)号：US10770303B2

公开(公告)日：2020-09-08

申请号：US16397439

申请日：2019-04-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/308 ,  G03F7/20 ,  G03F1/00 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/302 ,  H01L21/033 ,  H01L21/02

摘要： The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

公开(公告)号：US10410863B2

公开(公告)日：2019-09-10

申请号：US15852129

申请日：2017-12-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Wen-Chun Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/033 ,  H01L21/027 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3213

摘要： The present disclosure provides a method that includes forming a first pattern feature and a second pattern feature over a material layer by a first photolithographic process. The method also includes forming a first spacer feature on a sidewall of the first pattern feature and a second spacer feature on a sidewall of the second pattern feature. Additionally, the method includes forming a third pattern feature on the material layer between the first spacer feature and the second spacer feature by a second photolithographic process. In addition, the method includes removing the first and second spacer features to expose a portion of the material layer.

公开(公告)号：US10163654B2

公开(公告)日：2018-12-25

申请号：US15237898

申请日：2016-08-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Sung Yen ,  Chung-Ju Lee ,  Chun-Kuang Chen ,  Chia-Tien Wu ,  Ta-Ching Yu ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/8234

摘要： A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

公开(公告)号：US10032664B2

公开(公告)日：2018-07-24

申请号：US15174699

申请日：2016-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Chih-Ming Lai ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528 ,  H01L21/3213 ,  H01L23/522

摘要： The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.

公开(公告)号：US09991132B2

公开(公告)日：2018-06-05

申请号：US14689288

申请日：2015-04-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Yuan Tseng ,  Chi-Cheng Hung ,  Chun-Kuang Chen ,  De-Fang Chen ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Wei-Liang Lin

IPC分类号： H01L21/00 ,  H01L21/311 ,  H01L21/033

CPC分类号： H01L21/31144 ,  H01L21/0337

摘要： A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process.

公开(公告)号：US20170358566A1

公开(公告)日：2017-12-14

申请号：US15668930

申请日：2017-08-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L27/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L23/522 ,  H01L21/308 ,  H01L29/06

CPC分类号： H01L27/0207 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0657

摘要： Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a target layer disposed over the substrate. The target layer includes a first target feature, a second target feature, and a third target feature. The second target feature is spaced a first distance from the first target feature, and the third target feature is spaced a second distance from the first target feature. The first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process.

公开(公告)号：US09761436B2

公开(公告)日：2017-09-12

申请号：US14334904

申请日：2014-07-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/027 ,  H01L21/02 ,  H01L21/308 ,  G03F7/20 ,  G03F1/00 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/302 ,  H01L21/033

CPC分类号： H01L21/02071 ,  G03F1/144 ,  G03F7/70466 ,  H01L21/0337 ,  H01L21/302 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

公开(公告)号：US09747408B2

公开(公告)日：2017-08-29

申请号：US14832026

申请日：2015-08-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsu-Ting Huang ,  Ru-Gun Liu ,  Shuo-Yen Chou ,  Tsai-Sheng Gau

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F7/70433 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5009 ,  G06F17/5072 ,  G06F2217/12

摘要： The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes receiving an IC design layout; and performing an inverse beam technology (IBT) process to the IC design layout, thereby generating a final mask pattern, wherein the IBT process uses a single IBT model to simulate both a mask making process and a wafer making process.

公开(公告)号：US20160254191A1

公开(公告)日：2016-09-01

申请号：US14632979

申请日：2015-02-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Yuan Tseng ,  Chi-Cheng Hung ,  Chun-Kuang Chen ,  Chih-Ming Lai ,  Huan-Just Lin ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Wei-Liang Lin

IPC分类号： H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/3086 ,  H01L29/6653 ,  H01L29/6656

摘要： A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成多个第一间隔物。 多个第二间隔物的第二间隔物沉积在每个第一间隔物的侧壁上。 在一些实施例中，相邻的第一间隔件之间的间隔被配置为使得形成在相邻的第一间隔件的侧壁上的第二间隔物物理地合并以形成合并的第二间隔件。 可以执行第二间隔切割工艺以选择性地去除至少一个第二间隔物。 在一些实施例中，多个第三间隔件的第三间隔件形成在每个第二间隔件的侧壁上。 可以执行第三间隔切割工艺以选择性地去除至少一个第三间隔物。 在衬底上执行第一蚀刻工艺以形成鳍片区域。 在第一蚀刻工艺期间，多个第三间隔物掩盖衬底的部分。

公开(公告)号：US20160062250A1

公开(公告)日：2016-03-03

申请号：US14471653

申请日：2014-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Cheng Hung ,  Wei-Liang Lin ,  Yung-Sung Yen ,  Chun-Kuang Chen ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Tzung-Chi Fu ,  Ming-Sen Tung ,  Fu-Jye Liang ,  Li-Jui Chen ,  Meng-Wei Chen ,  Kuei-Shun Chen

IPC分类号： G03F7/20

CPC分类号： G03F7/70633 ,  G03F7/70258 ,  G03F7/705

摘要： The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.

摘要翻译： 本公开提供了一种方法。 该方法包括在图案化衬底上形成抗蚀剂层; 从图案化的衬底收集第一重叠数据; 基于来自所述图案化衬底的从所述集成电路（IC）图案到所述第一覆盖数据的第二覆盖数据的映射来确定覆盖补偿; 根据覆盖补偿对光刻系统进行补偿处理; 然后通过光刻系统对抗蚀剂层进行光刻曝光处理，从而将IC图案成像到抗蚀剂层。