公开(公告)号：US20220122890A1

公开(公告)日：2022-04-21

申请号：US17568114

申请日：2022-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting CHUNG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a fin element extending therefrom. In some embodiments, a gate structure is formed over the fin element, where the gate structure includes a dielectric layer on the fin element, a metal capping layer disposed over the dielectric layer, and a metal electrode formed over the metal capping layer. In some cases, first sidewall spacers are formed on opposing sidewalls of the metal capping layer and the metal electrode. In various embodiments, the dielectric layer extends laterally underneath the first sidewall spacers to form a dielectric footing region.

公开(公告)号：US20220093743A1

公开(公告)日：2022-03-24

申请号：US17027302

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments of the present disclosure provide semiconductor device structures having at least one T-shaped stacked nanosheet transistor to provide increased effective conductive area across the channel regions. In one embodiment, the semiconductor device structure includes a first channel layer formed of a first material, wherein the first channel layer has a first width, and a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer and the second channel layer, and a gate electrode layer disposed on the gate dielectric layer.

公开(公告)号：US20220093471A1

公开(公告)日：2022-03-24

申请号：US17027282

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shang-Wen CHANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

公开(公告)号：US20220037496A1

公开(公告)日：2022-02-03

申请号：US17302395

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin CHEN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66

Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

公开(公告)号：US20220037190A1

公开(公告)日：2022-02-03

申请号：US16943996

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L23/532

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer.

公开(公告)号：US20210296179A1

公开(公告)日：2021-09-23

申请号：US17303771

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning JU ,  Kuo-Cheng CHIANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/11 ,  H01L29/423 ,  H01L21/762

Abstract: A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.

公开(公告)号：US20210202715A1

公开(公告)日：2021-07-01

申请号：US17200226

申请日：2021-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Keng-Chu LIN ,  Shi-Ning JU

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, a gate structure, a plurality of source/drain structures, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin extends upwardly from the substrate. The second semiconductor fin extends upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The source/drain structures are on the first and second semiconductor fins. The STI oxide extends continuously between the first and second semiconductor fins and has a U-shaped profile when viewed in a cross section taken along a lengthwise direction of the gate structure. The dielectric layer is partially embedded in the STI oxide and has a U-shaped profile when viewed in the cross section taken along the lengthwise direction of the gate structure.

公开(公告)号：US20200381530A1

公开(公告)日：2020-12-03

申请号：US16426114

申请日：2019-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting CHUNG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/49 ,  H01L29/161 ,  H01L21/8234

Abstract: Multi-gate semiconductor devices and methods for forming thereof including forming air gaps between the gate and the adjacent source/drain features. A first fin element including a plurality of silicon layers is disposed on a substrate, a first gate structure is formed over a channel region of the first fin element. An air gap is formed such that it is disposed on a sidewall of the portion of the first gate structure. An epitaxial source/drain feature abuts the air gap. A portion of the first gate structure may also be disposed between first and second layers of the plurality of silicon layers.

公开(公告)号：US20200312847A1

公开(公告)日：2020-10-01

申请号：US16877261

申请日：2020-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L21/768

Abstract: A FinFET device includes a fin, an epitaxial layer disposed at a side surface of the fin, a contact disposed on the epitaxial layer and on the fin. The contact includes an epitaxial contact portion and a metal contact portion disposed on the epitaxial contact portion. The doping concentration of the epitaxial contact portion is higher than a doping concentration of the epitaxial layer.

公开(公告)号：US20200295155A1

公开(公告)日：2020-09-17

申请号：US16890803

申请日：2020-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/02

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.