公开(公告)号：US09135014B2

公开(公告)日：2015-09-15

申请号：US13397452

申请日：2012-02-15

Applicant: Thang M. Tran ,  Trinh Huy Nguyen

Inventor： Thang M. Tran ,  Trinh Huy Nguyen

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3855 ,  G06F9/30094 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851

Abstract: A data processing system comprises a processor unit that includes an instruction decode/issue unit including a re-order buffer having entries that include an execution queue tag that indicates an execution queue location of an instruction to which a re-order buffer entry is assigned, a result valid indicator to indicate that a corresponding instruction has executed with a status bit valid result, and a forward indicator to indicate that the status bit can be forwarded to an execution queue of an instruction pointed to that is waiting to receive the status bit.

Abstract translation: 一种数据处理系统，包括：处理器单元，其包括指令解码/发布单元，该指令解码/发布单元包括具有条目的重新排序缓冲器，所述条目包括指示分配了重新排序缓冲器条目的指令的执行队列位置的执行队列标签， 结果有效指示符，以指示相应的指令已经执行了状态位有效结果，以及前向指示符，以指示状态位可以被转发到指示正在等待接收状态位的指令的执行队列。

公开(公告)号：US08972700B2

公开(公告)日：2015-03-03

申请号：US13036251

申请日：2011-02-28

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

Abstract: An instruction unit provides instructions for execution by a processor. A decode unit decodes instructions received from the instruction unit. Queues are coupled to receive instructions from the decode unit. Each instruction in a same queue is executed in order by a corresponding execution unit. An arbiter is coupled to each queue and to the execution unit that executes instructions of a first instruction type. The arbiter selects a next instruction of the first instruction type from a bottom entry of the queue for execution by the first execution unit.

Abstract translation: 指令单元提供由处理器执行的指令。 解码单元解码从指令单元接收的指令。 队列被耦合以从解码单元接收指令。 同一个队列中的每个指令由相应的执行单元按顺序执行。 仲裁器耦合到执行第一指令类型的指令的每个队列和执行单元。 仲裁器从队列的底部条目中选择第一指令类型的下一条指令，以由第一执行单元执行。

公开(公告)号：US08966229B2

公开(公告)日：2015-02-24

申请号：US13212420

申请日：2011-08-18

Applicant: Thang M. Tran ,  Trinh Huy H. Nguyen

Inventor： Thang M. Tran ,  Trinh Huy H. Nguyen

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3891

Abstract: Processing systems and methods are disclosed that can include an instruction unit which provides instructions for execution by the processor; a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions; and a plurality of execution queues coupled to the decode/issue unit, wherein each issued instruction from the decode/issue unit can be stored into an entry of at least one queue of the plurality of execution queues. The plurality of queues can comprise an independent execution queue, a dependent execution queue, and a plurality of execution units coupled to receive instructions for execution from the plurality of execution queues. The plurality of execution units can comprise a first execution unit, coupled to receive instructions from the dependent execution queue and the independent execution queue which have been selected for execution. When a multi-cycle instruction at a bottom entry of the dependent execution queue is selected for execution, it may not be removed from the dependent execution queue until a result is received from the first execution unit. When a multi-cycle instruction at a bottom entry of the independent execution queue is selected for execution, it can be removed from the independent execution queue without waiting to receive a result from the first execution unit.

Abstract translation: 公开了可以包括提供由处理器执行的指令的指令单元的处理系统和方法; 解码/发布单元，其对从指令单元接收的指令进行解码并发出指令; 以及耦合到解码/发布单元的多个执行队列，其中来自解码/发布单元的每个发出的指令可以被存储到多个执行队列中的至少一个队列的条目中。 多个队列可以包括独立的执行队列，从属执行队列和多个执行单元，其耦合以从多个执行队列接收用于执行的指令。 多个执行单元可以包括第一执行单元，其被耦合以从已经被选择执行的从属执行队列和独立执行队列接收指令。 当从属执行队列的底部条目的多循环指令被选择执行时，直到从第一个执行单元接收到结果为止，它可能不会从依赖执行队列中删除。 当选择执行独立执行队列的底部条目的多循环指令时，可以从独立的执行队列中移除它，而不必等待从第一执行单元接收结果。

公开(公告)号：US08959371B2

公开(公告)日：2015-02-17

申请号：US13551220

申请日：2012-07-17

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3206

Abstract: A technique for performing power management for configurable processor resources of a processor determining whether to increase, decrease, or maintain resource units for each of the configurable processor resources based on utilization of each of the configurable processor resources. A total weighted power number for the processor is substantially maintained while resource units for each of the configurable processor resources whose utilization is above a first level is increased and resource units for each of the configurable processor resources whose utilization is below a second level is decreased. The total weighted power number corresponds to a sum of weighted power numbers for the configurable processor resources.

Abstract translation: 一种用于对处理器的可配置处理器资源执行电力管理的技术，其基于每个可配置处理器资源的利用来确定是否增加，减少或维护每个可配置处理器资源的资源单元。 基本上维持处理器的总加权功率数，同时利用率高于第一级的可配置处理器资源的每个可用处理器资源的资源单元被增加，并且其利用率低于第二级的每个可配置处理器资源的资源单元减少。 总加权功率数量对应于可配置处理器资源的加权功率数之和。

公开(公告)号：US08904150B2

公开(公告)日：2014-12-02

申请号：US13116325

申请日：2011-05-26

Applicant: Thang M. Tran ,  Leick D. Robinson

Inventor： Thang M. Tran ,  Leick D. Robinson

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC classification number: G06F9/3851 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838

Abstract: A processor includes an instruction unit which provides instructions for execution by the processor, a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions, and a plurality of execution queues coupled to the decode/issue unit. Each issued instruction from the decode/issue unit is stored into an entry of at least one queue of the plurality of execution queues, wherein each entry of the plurality of execution queues is configured to store an issued instruction and a duplicate indicator corresponding to the issued instruction which indicates whether or not a duplicate instruction of the issued instruction is also stored in an entry of another queue of the plurality of execution queues.

Abstract translation: 处理器包括提供由处理器执行的指令的指令单元，对从指令单元接收的指令进行解码并发出指令的解码/发布单元以及耦合到解码/发布单元的多个执行队列。 来自解码/发布单元的每个发出的指令被存储到多个执行队列中的至少一个队列的条目中，其中多个执行队列中的每个条目被配置为存储发出的指令和与发出的执行队列对应的重复指示符 指示所发出的指令的重复指令是否也存储在多个执行队列的另一个队列的条目中。

公开(公告)号：US08639884B2

公开(公告)日：2014-01-28

申请号：US13037013

申请日：2011-02-28

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/0842 ,  G06F9/30043 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3891 ,  G06F12/0848

Abstract: Systems and methods are disclosed for multi-threading computer systems. In a computer system executing multiple program threads in a processing unit, a first load/store execution unit is configured to handle instructions from a first program thread and a second load/store execution unit is configured to handle instructions from a second program thread. When the computer system executing a single program thread, the first and second load/store execution units are reconfigured to handle instructions from the single program thread, and a Level 1 (L1) data cache is reconfigured with a first port to communicate with the first load/store execution unit and a second port to communicate with the second load/store execution unit.

Abstract translation: 公开了用于多线程计算机系统的系统和方法。 在处理单元中执行多个程序线程的计算机系统中，第一加载/存储执行单元被配置为处理来自第一程序线程的指令，而第二加载/存储执行单元被配置为处理来自第二程序线程的指令。 当计算机系统执行单个程序线程时，重新配置第一和第二加载/存储执行单元以处理来自单个程序线程的指令，并且使用第一端口重新配置级别1（L1）数据高速缓存以与第一 加载/存储执行单元和第二端口与第二加载/存储执行单元通信。

公开(公告)号：US20120324209A1

公开(公告)日：2012-12-20

申请号：US13162835

申请日：2011-06-17

Applicant: Thang M. Tran ,  Edmund J. Gieske ,  Michael B. Schinzler

Inventor： Thang M. Tran ,  Edmund J. Gieske ,  Michael B. Schinzler

IPC: G06F9/38

CPC classification number: G06F9/3806

Abstract: A data processor includes a branch target buffer (BTB) having a plurality of BTB entries grouped in ways. The BTB entries in one of the ways include a short tag address and the BTB entries in another one of the ways include a full tag address.

Abstract translation: 数据处理器包括具有以方式分组的多个BTB条目的分支目标缓冲器（BTB）。 其中一种方式的BTB条目包括一个短标签地址，而另一种方式的BTB条目包括一个完整的标签地址。

公开(公告)号：US20120278596A1

公开(公告)日：2012-11-01

申请号：US13094110

申请日：2011-04-26

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/312

CPC classification number: G06F9/384 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3863

Abstract: A data processing device maintains register map information that maps accesses to architectural registers, as identified by instructions being executed, to physical registers of the data processing device. In response to determining that an instruction, such as a speculatively-executing conditional branch, indicates a checkpoint, the data processing device stores the register map information for subsequent retrieval depending on the resolution of the instruction. In addition, in response to the checkpoint indication the data processing device generates new register map information such that accesses to the architectural registers are mapped to different physical registers. The data processing device maintains a list, referred to as a free register list, of physical registers available to be mapped to an architectural registers.

Abstract translation: 数据处理设备维护寄存器映射信息，其将对正在执行的指令识别的架构寄存器的访问映射到数据处理设备的物理寄存器。 响应于确定诸如推测执行条件分支的指令指示检查点，数据处理设备根据指令的分辨率存储用于后续检索的寄存器映射信息。 此外，响应于检查点指示，数据处理装置产生新的寄存器映射信息，使得对架构寄存器的访问被映射到不同的物理寄存器。 数据处理设备维护被称为自由寄存器列表的可被映射到架构寄存器的物理寄存器的列表。

公开(公告)号：US07266676B2

公开(公告)日：2007-09-04

申请号：US10394820

申请日：2003-03-21

Applicant: Thang M. Tran ,  Ravi Pratap Singh ,  Deepa Duraiswamy ,  Srikanth Kannan

Inventor： Thang M. Tran ,  Ravi Pratap Singh ,  Deepa Duraiswamy ,  Srikanth Kannan

IPC: G06F9/42

CPC classification number: G06F9/3806 ,  G06F9/3804 ,  G06F9/3844

Abstract: Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the tag array provides an index to a corresponding entry in the data array, storing in a selected entry in the tag array information representative of a branch target of a current branch instruction, storing in a corresponding entry in the data array information representative of a branch target of a next branch instruction, and providing the information representative of the branch target of the next branch instruction in response to a match to an entry in the tag array. The information representative of the branch target of the next branch instruction may include a taken branch target address of the next branch instruction and an offset value. The offset value may represent an address of a next sequential instruction following the next branch instruction.

Abstract translation: 在数字处理器中提供用于分支预测的方法和装置。 一种方法包括提供具有标签阵列和数据阵列的分支目标缓冲器，其中标签阵列中的每个条目向数据阵列中的对应条目提供索引，将代表数据阵列的标签阵列信息中的选定条目存储 当前分支指令的目标，存储在表示下一分支指令的分支目标的数据阵列信息中的对应条目中，并且响应于与条目的匹配来提供表示下一分支指令的分支目标的信息 在标签数组中。 代表下一个分支指令的分支目标的信息可以包括下一个分支指令的取得分支目标地址和偏移值。 偏移值可以表示下一个分支指令之后的下一个顺序指令的地址。

公开(公告)号：US06367006B1

公开(公告)日：2002-04-02

申请号：US09619986

申请日：2000-07-20

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F942

CPC classification number: G06F9/382 ,  G06F9/30152 ,  G06F9/3816

Abstract: A prefetch/predecode unit includes one or more prefetch buffers which are configured to store prefetched sets of instruction bytes and corresponding predecode data. Additionally, each prefetch buffer is configured to store a predecode byte pointer. The predecode byte pointer indicates the byte within the corresponding prefetched set of instruction bytes at which predecoding is to be initiated. Predecoding may be resumed within a given prefetch buffer if predecoding thereof is interrupted to predecode a different set of instruction bytes (e.g. a set of instruction bytes fetched from the instruction cache).

Abstract translation: 预取/预解码单元包括一个或多个预取缓冲器，其被配置为存储预取指令字节集合和相应的预代码数据。 另外，每个预取缓冲器被配置为存储预解码字节指针。 预代码字节指针指示在要启动预解码的相应预取指令字节集合内的字节。 如果其预解码被中断以预先解码不同的指令字节集合（例如，从指令高速缓存取出的一组指令字节），则可以在给定的预取缓冲器内恢复预解码。