公开(公告)号：US06505296B2

公开(公告)日：2003-01-07

申请号：US09521160

申请日：2000-03-08

申请人： Dale C. Morris ,  Jonathan K. Ross ,  James O. Hays ,  Jerome C. Huck

发明人： Dale C. Morris ,  Jonathan K. Ross ,  James O. Hays ,  Jerome C. Huck

IPC分类号： G06F942

CPC分类号： G06F9/3834 ,  G06F8/445 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3861 ,  G06F11/1407

摘要： A computer system includes a processor for executing a program and an interruption handler from a memory. The processor includes an instruction pointer indicating a memory location of a current executing instruction. The processor executes a trampoline check instruction in the program which tests a condition and if the condition is true, causes an interruption and supplies an address displacement. The interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of a special handler in the program. The restart point is a sum of the address displacement and a value of the instruction pointer at the time of the interruption. If the condition is false, normal control flow of the program is continued.

公开(公告)号：US06760835B1

公开(公告)日：2004-07-06

申请号：US09721079

申请日：2000-11-22

申请人： Elaine Y. Yu

发明人： Elaine Y. Yu

IPC分类号： G06F942

CPC分类号： G06F9/3844 ,  G06F9/3804 ,  G06F9/3861

摘要： A method and an architecture for recovery from a branch misprediction in a processor. The method may include the steps of (A) evaluating a branch prediction for a branch instruction, (B) pausing an instruction cache line fetch in response to the branch instruction, and (C) resuming the instruction cache line fetch from where paused in response to evaluating the branch prediction as incorrect to recover from the branch misprediction.

摘要翻译： 一种用于从处理器中的分支错误预测中恢复的方法和架构。 该方法可以包括以下步骤：（A）评估分支指令的分支预测，（B）响应于分支指令暂停指令高速缓存线取出，以及（C）从响应中暂停的指令高速缓存线提取恢复 评估分支预测是不正确的，从分支错误预测中恢复。

公开(公告)号：US06247122B1

公开(公告)日：2001-06-12

申请号：US09203884

申请日：1998-12-02

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F942

CPC分类号： G06F9/3846 ,  G06F9/3848

摘要： An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A static branch predictor makes a prediction of the outcome of a conditional branch instruction based on the branch test type and the branch target address displacement sign. A branch history table stores a bit indicating whether the prediction of the static predictor agreed with the outcome of the last execution of the branch instruction. If the history table bit agrees, then the static prediction is used. Otherwise, the opposite of the static prediction is used.

摘要翻译： 提供了一种通过提高条件分支指令的预测精度来提高微处理器性能的装置和方法。 静态分支预测器基于分支测试类型和分支目标地址位移符号来预测条件分支指令的结果。 分支历史表存储指示静态预测符的预测是否与分支指令的最后执行的结果一致的位。 如果历史表位同意，则使用静态预测。 否则，使用静态预测的相反。

公开(公告)号：US06237088B1

公开(公告)日：2001-05-22

申请号：US09089736

申请日：1998-06-03

申请人： Nazar A. Zaidi

发明人： Nazar A. Zaidi

IPC分类号： G06F942

CPC分类号： G06F9/3812

摘要： An apparatus, system and method are described for tracking in-flight line addresses. Such tracking enables a determination of a self-modifying code (SMC) conflict. In one embodiment, the apparatus comprises a line address buffer and companion logic. The line address buffer contains a first plurality of line addresses. Each line address is associated with a fetched instruction pointer. The comparison logic compares a second plurality of line addresses with an address of an instruction being executed in order to detect an event.

摘要翻译： 描述了用于跟踪飞行中线路地址的装置，系统和方法。 这种跟踪使得能够确定自修改代码（SMC）冲突。 在一个实施例中，该装置包括行地址缓冲器和伴随逻辑。 行地址缓冲器包含第一多行行地址。 每个行地址与获取的指令指针相关联。 比较逻辑将第二多个行地址与正在执行的指令的地址进行比较，以便检测事件。

公开(公告)号：US06553426B2

公开(公告)日：2003-04-22

申请号：US08944326

申请日：1997-10-06

申请人： Urs Hölzle ,  Robert Griesemer

发明人： Urs Hölzle ,  Robert Griesemer

IPC分类号： G06F942

CPC分类号： G06F9/4486

摘要： Methods and apparatus for efficiently enabling an alternate return address associated with a function call to essentially be stored such that the alternate return address may be readily accessed are disclosed. According to one aspect of the present invention, a method for enabling a return address associated with a function called by a routine to be efficiently stored includes calling the function from within the routine while the routine is executing. In general, the function is external to the routine. The function, once called, begins executing. Eventually, the function returns to the routine. Specifically, the function returns to a location in the routine that is identified by an expected return point, or normal return address. The instruction in the routine that corresponds to the expected return point is a dummy instruction that executes with a low computational overhead but does not affect program execution. When the called function is to return to an alternate return point, it obtains the address by reading data embedded in the dummy instruction.

摘要翻译： 公开了用于有效地实现与函数调用相关联的替代返回地址的方法和装置，以基本上被存储，使得可以容易地访问替代返回地址。 根据本发明的一个方面，一种用于使与由程序调用的函数相关联的返回地址能够被有效存储的方法包括在程序执行期间从该例程中调用该函数。 一般情况下，该函数在程序外部。 该函数一旦被调用，就开始执行。 最终，函数返回到例程。 具体来说，该函数返回到由预期返回点或正常返回地址标识的例程中的位置。 程序中对应于预期返回点的指令是以低计算开销执行但不影响程序执行的虚拟指令。 当被叫函数返回到交替返回点时，通过读取嵌入在虚拟指令中的数据来获取地址。

公开(公告)号：US06526503B1

公开(公告)日：2003-02-25

申请号：US09434763

申请日：1999-11-04

申请人： Balaram Sinharoy

发明人： Balaram Sinharoy

IPC分类号： G06F942

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3863 ,  G06F9/4486

摘要： Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address for accessing a corresponding instruction in a memory device. A counter generates a pointer to an entry in an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks. Selector circuitry selects the active one of the logical stacks in accordance with the performance of the Push and Pop operations.

摘要翻译： 指令分支电路，其包括多个逻辑堆栈，每个逻辑堆栈具有多个条目，用于存储访问存储器设备中相应指令的地址。 计数器产生指向逻辑堆栈中的活动的一个条目中的条目的指针，该计数器包括递增逻辑，其在按压操作之后增加存储的指针值，并且在弹出操作之后将存储的指针值递减到逻辑的活动的一个之后的递减逻辑 堆栈 选择器电路根据Push和Pop操作的性能选择活动的逻辑堆栈。

公开(公告)号：US06526463B1

公开(公告)日：2003-02-25

申请号：US09548988

申请日：2000-04-14

申请人： Zhimin Ding ,  Gregory K. Goodhue ,  Ata R. Khan

发明人： Zhimin Ding ,  Gregory K. Goodhue ,  Ata R. Khan

IPC分类号： G06F942

CPC分类号： G06F9/342 ,  G06F9/30043 ,  G06F9/30163 ,  G06F9/30189 ,  G06F9/4486 ,  G06F9/4812

摘要： A processing system with extended addressing capabilities includes a control bit that controls the number of address bytes that are stored onto a program stack. If the control bit is set to a first state, the address is pushed onto the program stack in the same manner as that used for shorter-address legacy devices. If the control bit is set to a second state, the address is pushed onto the program stack using the number of bytes required to contain a longer extended address. This same control bit controls the number of bytes that are popped off the stack upon return from an interrupt subroutine. The state of the control bit is controlled by one or more program instructions, thereby allowing it to assume each state dynamically. This dynamic control of the number of bytes pushed and popped to and from the stack allows for an optimization of stack utilization, and thereby further compatibility with legacy devices and applications.

摘要翻译： 具有扩展寻址能力的处理系统包括控制位，该控制位控制存储在程序堆栈上的地址字节数。 如果控制位设置为第一状态，则以与用于较短地址的传统设备相同的方式将地址推送到程序堆栈。 如果控制位设置为第二个状态，则使用包含较长扩展地址所需的字节数将该地址推送到程序堆栈。 相同的控制位控制从中断子程序返回时从堆栈弹出的字节数。 控制位的状态由一个或多个程序指令控制，从而允许其动态地呈现每个状态。 对堆栈和从堆栈进行弹出的字节数的这种动态控制允许优化堆栈利用率，从而进一步与传统设备和应用程序的兼容性。

公开(公告)号：US06314514B1

公开(公告)日：2001-11-06

申请号：US09271591

申请日：1999-03-18

申请人： Thomas C. McDonald

发明人： Thomas C. McDonald

IPC分类号： G06F942

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/4486

摘要： An apparatus and method for correcting a call/return stack internal to a microprocessor is provided. In the case of a call, the microprocessor pushes the return address onto the internal call/return stack and in the case of a return, the microprocessor pops the return address from the internal call/return stack into the instruction register. However, prior to speculative execution of the call or return, the correction apparatus stores correction information to enable correction of the internal call/return stack. If the conditional branch instruction was mispredicted, the correction apparatus corrects the internal call/return stack based on the correction information previously stored. The correction information is stored in stack memories so that corrections can be made in the reverse order of which the incorrect modifications to the internal call/return stack were made. This enables correction of the internal call/return stack even if multiple call or return instructions have been speculatively executed prior to resolution of the conditional branch.

摘要翻译： 提供了一种用于校正微处理器内部的呼叫/返回堆栈的装置和方法。 在通话的情况下，微处理器将返回地址推送到内部呼叫/返回栈，并且在返回的情况下，微处理器将返回地址从内部呼叫/返回堆栈弹出到指令寄存器中。 然而，在推测执行呼叫或返回之前，校正装置存储校正信息以使内部呼叫/返回栈的校正。 如果条件分支指令被错误预测，则校正装置基于先前存储的校正信息来校正内部呼叫/返回栈。 校正信息存储在堆栈存储器中，使得可以以与内部呼叫/返回堆栈的不正确修改相反的顺序进行校正。 即使在分解条件分支之前已经推测性地执行了多个调用或返回指令，也能够修正内部的调用/返回栈。

公开(公告)号：US06308263B1

公开(公告)日：2001-10-23

申请号：US09429022

申请日：1999-10-29

申请人： Hiroshi Hayakawa ,  Harutsugu Fukumoto ,  Hiroaki Tanaka

发明人： Hiroshi Hayakawa ,  Harutsugu Fukumoto ,  Hiroaki Tanaka

IPC分类号： G06F942

CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F9/30167

摘要： A decoder decodes a branch instruction. An operating section executes logical, arithmetic, and shift operations. A register file store operation result of the operating section. A program counter counting the address of the present programs. A direct-setting bus is provided to allowing the decoder to directly set an immediate value to the program counter without passing through an output bus of the operating section. And, a switch selectively connects the direct-setting bus or the output bus to the program counter.

摘要翻译： 解码器解码分支指令。 操作部分执行逻辑，算术和移位操作。 操作部分的注册文件存储操作结果。 一个程序计数器，用于计数当前程序的地址。 提供直接设置总线以允许解码器直接将程序计数器设置为不经过操作部分的输出总线的程序计数器。 而且，开关选择性地将直接设置总线或输出总线连接到程序计数器。

公开(公告)号：US06618799B2

公开(公告)日：2003-09-09

申请号：US10198905

申请日：2002-07-19

申请人： Erik E. Hagersten

发明人： Erik E. Hagersten

IPC分类号： G06F942

CPC分类号： G06F11/0712 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0766 ,  G06F12/0284 ,  G06F12/0864 ,  G06F12/1018 ,  G06F12/1072 ,  G06F2212/2542 ,  G06F2212/272

摘要： A multiprocessing computer system employs local and global address spaces and multiple access modes. A portion of the global memory of the multiprocessing computer system is allocated to each node, called local memory space. Two logical address spaces are mapped to the local memory of each node. A coherent memory replication (CMR) address space stores shadow pages of data from remote nodes and a local address space stores local data. A bit within a local physical address identifies whether data is a shadow page, which is stored in CMR space, or local data, which is stored in local address space. When a transaction requiring a coherency operation is performed, the CMR bit indicates whether a local physical address to global address translation is required. In one embodiment, if the CMR bit is clear, the local physical address is the same as the global address and the local physical address is used for the coherency operation. Alternatively, if the CMR bit is set, the local physical address is translated to a global address during the coherency operation.