公开(公告)号：US08407384B2

公开(公告)日：2013-03-26

申请号：US13300838

申请日：2011-11-21

申请人： Akio Nakajima

发明人： Akio Nakajima

IPC分类号： G06F13/38

CPC分类号： G06F3/0664 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0658 ,  G06F3/067 ,  G06F13/40 ,  H04L67/1097

摘要： This disk array subsystem includes a data input/output unit for inputting and outputting data in and from the network, a connecting unit for connecting the data input/output unit and a plurality of storage apparatuses, and a control unit for controlling the input and output of data in and from the network. The control unit includes a logical link setting unit for zoning at least one or more physical links among a plurality of physical links for inputting and outputting data between the data input/output unit and the connecting unit, or between the connecting unit and the connecting unit into at least one or more logical links, and setting a plurality of logical links to one physical link; and a link unit for simultaneously multiplexing the data to a plurality of the logical links set with the logical link setting unit, and linking the data to the physical link.

摘要翻译： 该磁盘阵列子系统包括用于在网络中输入和输出数据的数据输入/输出单元，用于连接数据输入/输出单元和多个存储装置的连接单元，以及用于控制输入和输出的控制单元 的数据进出网络。 控制单元包括逻辑链路设置单元，用于在数据输入/输出单元和连接单元之间或连接单元和连接单元之间的多个物理链路之间进行数据输入和输出中的至少一个或多个物理链路的分区 至少一个或多个逻辑链路，并将多个逻辑链路设置为一个物理链路; 以及链路单元，用于将数据同时复用到由逻辑链路设置单元设置的多个逻辑链路，并将数据链接到物理链路。

公开(公告)号：US08086773B2

公开(公告)日：2011-12-27

申请号：US11968766

申请日：2008-01-03

申请人： Akio Nakajima

发明人： Akio Nakajima

IPC分类号： G06F13/38

CPC分类号： G06F3/0664 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0658 ,  G06F3/067 ,  G06F13/40 ,  H04L67/1097

摘要： This disk array subsystem includes a data input/output unit for inputting and outputting data in and from the network, a connecting unit for connecting the data input/output unit and a plurality of storage apparatuses, and a control unit for controlling the input and output of data in and from the network. The control unit includes a logical link setting unit for zoning at least one or more physical links among a plurality of physical links for inputting and outputting data between the data input/output unit and the connecting unit, or between the connecting unit and the connecting unit into at least one or more logical links, and setting a plurality of logical links to one physical link; and a link unit for simultaneously multiplexing the data to a plurality of the logical links set with the logical link setting unit, and linking the data to the physical link.

摘要翻译： 该磁盘阵列子系统包括用于在网络中输入和输出数据的数据输入/输出单元，用于连接数据输入/输出单元和多个存储装置的连接单元，以及用于控制输入和输出的控制单元 的数据进出网络。 控制单元包括逻辑链路设置单元，用于在数据输入/输出单元和连接单元之间或连接单元和连接单元之间的多个物理链路之间进行数据输入和输出中的至少一个或多个物理链路的分区 至少一个或多个逻辑链路，并将多个逻辑链路设置为一个物理链路; 以及链路单元，用于将数据同时复用到由逻辑链路设置单元设置的多个逻辑链路，并将数据链接到物理链路。

公开(公告)号：US07831764B2

公开(公告)日：2010-11-09

申请号：US12007329

申请日：2008-01-09

申请人： Akio Nakajima ,  Kentaro Shimada ,  Shuji Nakamura ,  Nagamasa Mizushima

发明人： Akio Nakajima ,  Kentaro Shimada ,  Shuji Nakamura ,  Nagamasa Mizushima

IPC分类号： G06F13/10

CPC分类号： G06F12/0246 ,  G06F11/108 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/262 ,  G06F2212/285 ,  G06F2212/7202 ,  G06F2212/7208

摘要： Provided is a storage system having a storage device including memory drives formed of the non-volatile memory, a group is constituted by the memory drives whose number is larger than the number of memory drives necessary to provide the memory capacity, the divided storage areas are managed in each of segments that includes at least one of the divided storage areas, the data storage area or the temporary storage area is allocated to the divided storage areas, upon receiving a data write request, the data storage area in which the write data is written and the segment are specified, the updated data is written in the temporary storage area included in the specified segment, the temporary storage area in which the data is written is set as a new data storage area, and data stored in the data storage area is erased and set as a new temporary storage area.

摘要翻译： 提供一种具有存储装置的存储系统，包括由非易失性存储器形成的存储器驱动器，该组由数量大于提供存储器容量所需的存储器驱动器的数量的存储器驱动器构成，分割的存储区域 在包含分割存储区域中的至少一个的段的每个段中管理，数据存储区域或临时存储区域在接收到数据写入请求时被分配给划分的存储区域，写入数据是 写入并且段被指定，更新的数据被写入包括在指定段中的临时存储区域中，将写入数据的临时存储区域设置为新的数据存储区域，并且存储在数据存储区域中的数据 被删除并设置为新的临时存储区域。

公开(公告)号：US20080297095A1

公开(公告)日：2008-12-04

申请号：US12153930

申请日：2008-05-28

申请人： Kazuyuki Aono ,  Akio Nakajima

发明人： Kazuyuki Aono ,  Akio Nakajima

IPC分类号： H02P25/02

CPC分类号： H02P6/10

摘要： Even when there is some degree of variation in the characteristics among components constituting a polyphase motor and a driving circuit therefor, current control signals of respective phases being input to the drive circuit have their amplitude finely adjusted by an amplitude control circuit, so that amplitude is uniform among armature currents of respective phases that are ultimately output from the drive circuit. The amplitude adjusting circuit is configured by gain variable amplifiers, for example. Thus, rotation fluctuation and vibration of the polyphase motor can be reduced.

摘要翻译： 即使当构成多相电动机的部件和其驱动电路之间的特性存在某种程度的变化时，输入到驱动电路的各相的电流控制信号也由振幅控制电路进行微调，使振幅为 在从驱动电路最终输出的各相的电枢电流之间是均匀的。 幅度调整电路例如由增益可变放大器构成。 因此，可以降低多相电机的旋转波动和振动。

公开(公告)号：US07420695B2

公开(公告)日：2008-09-02

申请号：US10103836

申请日：2002-03-25

申请人： Kazuyuki Kawabata ,  Akio Nakajima ,  Toshihisa Motosugi ,  Kenichi Matsumoto

发明人： Kazuyuki Kawabata ,  Akio Nakajima ,  Toshihisa Motosugi ,  Kenichi Matsumoto

IPC分类号： G06K15/00 ,  G06F3/12

CPC分类号： H04N1/32507 ,  H04N1/32502 ,  H04N1/32545 ,  H04N2201/0081

摘要： Allocation reading is started when an allocation origin image processing apparatus sends an allocation reading start alert. An image processing apparatus which received the allocation reading start alert, i.e., the allocation destination image processing apparatus, displays a continue reading specification key on its own display for user specification to continue reading by the allocation reading function. Continue reading is started by user operation of this continue reading specification key. That is, when a document image is read by the allocation destination image processing apparatus, the image data are transmitted to the allocation origin image processing apparatus. Then, the allocation origin image processing apparatus integrates the received image data with the image data read by the allocation origin image processing apparatus.

摘要翻译： 当分配原始图像处理装置发送分配读取开始警报时，开始分配读取。 接收到分配读取开始警报的图像处理装置，即分配目的地图像处理装置，在其自己的显示器上显示用于用户指定的连续读取指定键，以通过分配读取功能继续读取。 继续读取是由用户操作的这个继续读取规范键开始的。 也就是说，当文件图像被分配目的地图像处理装置读取时，图像数据被发送到分配原始图像处理装置。 然后，分配原始图像处理装置将接收到的图像数据与由分配原始图像处理装置读取的图像数据进行积分。

公开(公告)号：US20080201392A1

公开(公告)日：2008-08-21

申请号：US12007329

申请日：2008-01-09

申请人： Akio Nakajima ,  Kentaro Shimada ,  Shuji Nakamura ,  Nagamasa Mizushima

发明人： Akio Nakajima ,  Kentaro Shimada ,  Shuji Nakamura ,  Nagamasa Mizushima

IPC分类号： G06F12/02 ,  G06F17/30

CPC分类号： G06F12/0246 ,  G06F11/108 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/262 ,  G06F2212/285 ,  G06F2212/7202 ,  G06F2212/7208

摘要： Provided is a storage system having a storage device including memory drives formed of the non-volatile memory, a group is constituted by the memory drives whose number is larger than the number of memory drives necessary to provide the memory capacity, the divided storage areas are managed in each of segments that includes at least one of the divided storage areas, the data storage area or the temporary storage area is allocated to the divided storage areas, upon receiving a data write request, the data storage area in which the write data is written and the segment are specified, the updated data is written in the temporary storage area included in the specified segment, the temporary storage area in which the data is written is set as a new data storage area, and data stored in the data storage area is erased and set as a new temporary storage area.

摘要翻译： 提供一种具有存储装置的存储系统，包括由非易失性存储器形成的存储器驱动器，该组由数量大于提供存储器容量所需的存储器驱动器的数量的存储器驱动器构成，分割的存储区域 在包含分割存储区域中的至少一个的段的每个段中管理，数据存储区域或临时存储区域在接收到数据写入请求时被分配给划分的存储区域，写入数据是 写入并且段被指定，更新的数据被写入包括在指定段中的临时存储区域中，将写入数据的临时存储区域设置为新的数据存储区域，并且存储在数据存储区域中的数据 被删除并设置为新的临时存储区域。

公开(公告)号：US07382511B2

公开(公告)日：2008-06-03

申请号：US11295508

申请日：2005-12-07

申请人： Akio Nakajima

发明人： Akio Nakajima

IPC分类号： G02F1/03

CPC分类号： H03K17/941

摘要： A light modulation type photointerrupter includes: a light source that emits a light pulse to a transit area where an object transits; a driving circuit that drives the light source to emit the light pulse; a photoreceptor that converts the light pulse from the transit area into a pulse current and outputs the pulse current; an integrating circuit that integrates a pulse signal resulting from the pulse current and outputs a result of the integration, the integrating circuit having different time constants at a rise and at a fall of the pulse signal; and a detecting circuit that detects, based upon the output from the integrating circuit, presence or absence of the object in the transit area. The light source is driven to emit a pulse, which reduces the loss of power in the light emitter and the consumption of the current.

摘要翻译： 光调制型光电断路器包括：向对象转移的传送区域发射光脉冲的光源; 驱动光源以发射光脉冲的驱动电路; 将来自运送区域的光脉冲转换为脉冲电流并输出脉冲电流的感光体; 积分电路，其对由脉冲电流产生的脉冲信号进行积分，并输出积分的结果，积分电路在脉冲信号的上升和下降时具有不同的时间常数; 以及检测电路，其基于所述积分电路的输出来检测所述运送区域中的物体的存在或不存在。 光源被驱动以发射脉冲，这减少了光发射器中的功率损耗和电流的消耗。

公开(公告)号：US20070271481A1

公开(公告)日：2007-11-22

申请号：US11453434

申请日：2006-06-14

申请人： Norihiko Kawakami ,  Akio Nakajima

发明人： Norihiko Kawakami ,  Akio Nakajima

IPC分类号： G06F11/00

CPC分类号： G06F11/2092 ,  G06F11/0727 ,  G06F11/0757 ,  G06F11/076 ,  G06F11/1443

摘要： Provided is a storage control unit capable of, even when a failure occurs in access from a control unit to storage devices and the access from the control unit to the storage devices is switched to access via an alternate path, continuing I/O access to the storage devices without interrupting I/O requests from a host.The present invention provides a storage control unit having dual control units wherein a controller in one control unit, that has received an I/O request from a host, issues an I/O request to an initiator in another control unit using a control path between the controllers in the control units, and the initiator that has received this I/O request accesses the target storage device(s) via a connection path based on that I/O request.

摘要翻译： 提供了一种存储控制单元，即使当从控制单元访问到存储设备时发生故障，并且从控制单元到存储设备的访问被切换到经由备用路径的访问，继续I / O访问 存储设备，而不会中断来自主机的I / O请求。 本发明提供一种具有双重控制单元的存储控制单元，其中一个控制单元中已经从主机接收到I / O请求的控制器使用第二控制单元之间的控制路径向另一个控制单元中的启动器发出I / O请求 控制单元中的控制器和接收到该I / O请求的发起者基于该I / O请求经由连接路径访问目标存储设备。

公开(公告)号：US20070220204A1

公开(公告)日：2007-09-20

申请号：US11414675

申请日：2006-04-27

申请人： Akio Nakajima ,  Ikuya Yagisawa

发明人： Akio Nakajima ,  Ikuya Yagisawa

IPC分类号： G06F12/16 ,  G06F12/00

CPC分类号： G06F3/0635 ,  G06F3/0607 ,  G06F3/0613 ,  G06F3/0631 ,  G06F3/0637 ,  G06F3/0661 ,  G06F3/067 ,  G06F3/0689

摘要： The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

摘要翻译： 本发明的计算机系统具有多个SAS目标设备，SAS启动器设备和服务递送子系统，其通过物理连接物理连接并连接到SAS启动器设备连接到每个SAS目标设备 通过由多个物理链路构成的宽链路。 SAS启动器设备控制宽链路中的物理链路被分配给特定的SAS目标设备，借此，通过分配给SAS目标设备的物理链路从SAS启动器设备到SAS目标设备的访问， 不是通过未分配给SAS目标设备的物理链路进行的。

公开(公告)号：US06803795B2

公开(公告)日：2004-10-12

申请号：US10645661

申请日：2003-08-22

申请人： Akio Nakajima ,  Kohichi Furuta ,  Takao Matsui

发明人： Akio Nakajima ,  Kohichi Furuta ,  Takao Matsui

IPC分类号： H03K522

CPC分类号： H03F3/45085 ,  H03F2203/45594 ,  H03F2203/45596 ,  H03F2203/45601 ,  H03F2203/45652 ,  H03F2203/45691 ,  H03F2203/45696 ,  H03F2203/45722

摘要： A comparator circuit includes a differential amplifier including load resistors, for amplifying difference between two input voltages of the comparator circuit; an emitter follower circuit for applying positive feedback with respect to a differential amplifier and outputting an output voltage of the comparator circuit; and a grounded-base amplifier, and outputting an output voltage of the comparator circuit, for realizing both voltage output and current output. A grounded-base amplifier includes two transistors each of which has a base supplied with a reference voltage. The differential amplifier includes two load resistors respectively connected to each emitter of the transistors of the grounded-base amplifier. The load resistor flowing a current which is obtained through a collector of the transistor as an output current of the comparator. With this arrangement, it is not necessary to provide a current switch circuit for obtaining current output of the comparator circuit.