公开(公告)号：US11508839B2

公开(公告)日：2022-11-22

申请号：US17315380

申请日：2021-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/762 ,  H01L29/20 ,  H01L29/66

Abstract: A method of fabricating high electron mobility transistor, including the steps of providing a substrate with active areas, forming a buffer layer, a channel layer and a barrier layer sequentially on the substrate and gate, source and drain on the barrier layer, forming a trench surrounding the channel layer and the barrier layer, and forming a trench isolation structure in the trench, wherein the trench isolation structure applies stress on the channel layer and the barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor.

公开(公告)号：US20220302384A1

公开(公告)日：2022-09-22

申请号：US17834909

申请日：2022-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L45/00

Abstract: A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device.

公开(公告)号：US11450766B2

公开(公告)日：2022-09-20

申请号：US17315346

申请日：2021-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/762 ,  H01L29/20 ,  H01L29/66

Abstract: A high electron mobility transistor, including an active area, a buffer layer on the active area, a channel layer on the buffer layer, a barrier layer on the channel layer, and gate, source and drain on the barrier layer, and a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension hole gas (2DHG) of the high electron mobility transistor.

公开(公告)号：US11444196B2

公开(公告)日：2022-09-13

申请号：US17120243

申请日：2020-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L21/033 ,  H01L29/66 ,  H01L29/08 ,  H01L21/324 ,  H01L21/225 ,  H01L21/306 ,  H01L29/10

Abstract: A method of forming a semiconductor structure includes: providing a substrate including an upper surface, a gate structure disposed on the upper surface, a spacer disposed on a sidewall of the gate structure, a first region in the substrate, and a second region in the substrate; masking the second region and amorphizing the first region, such that an amorphous layer is formed in the first region; depositing a stress layer on the substrate, wherein the stress layer conformally covers the gate structure, the spacer, the first region and the second region; and recrystallizing the amorphous layer, thereby forming a dislocation in the first region.

公开(公告)号：US11387412B2

公开(公告)日：2022-07-12

申请号：US17024680

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L45/00

Abstract: A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device.

公开(公告)号：US20220165873A1

公开(公告)日：2022-05-26

申请号：US17153844

申请日：2021-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L21/285 ,  H01L29/66

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A gate is disposed on the second III-V compound layer. The gate includes a first P-type III-V compound layer, an undoped III-V compound layer and an N-type III-V compound layer are deposited from bottom to top. The first P-type III-V compound layer, the undoped III-V compound layer, the N-type III-V compound layer and the first III-V compound layer are chemical compounds formed by the same group III element and the same group V element. A drain electrode is disposed at one side of the gate. A drain electrode is disposed at another side of the gate. A gate electrode is disposed directly on the gate.

公开(公告)号：US20210280705A1

公开(公告)日：2021-09-09

申请号：US17315346

申请日：2021-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/762 ,  H01L29/20 ,  H01L29/66

Abstract: A high electron mobility transistor, including an active area, a buffer layer on the active area, a channel layer on the buffer layer, a barrier layer on the channel layer, and gate, source and drain on the barrier layer, and a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension hole gas (2DHG) of the high electron mobility transistor.

公开(公告)号：US11038046B2

公开(公告)日：2021-06-15

申请号：US16527042

申请日：2019-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/762 ,  H01L29/20 ,  H01L29/66

Abstract: A high electron mobility transistor, including an active area, a buffer layer on the active area, a channel layer on the buffer layer, a barrier layer on the channel layer, and gate, source and drain on the barrier layer, and a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor.

公开(公告)号：US10985271B2

公开(公告)日：2021-04-20

申请号：US16411053

申请日：2019-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US20200220027A1

公开(公告)日：2020-07-09

申请号：US16819148

申请日：2020-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L27/088 ,  H01L27/12 ,  H01L27/092 ,  H01L29/423

Abstract: A nanowire transistor structure includes a substrate. A first nanowire is suspended on the substrate. A first gate line crosses and surrounds the first nanowire. The first gate line includes a first end and a second end. A second gate line crosses and surrounds the first nanowire. The second gate line includes a third end and a fourth end. An interlayer dielectric encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.