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公开(公告)号：US11462086B2
公开(公告)日：2022-10-04
申请号：US17207073
申请日：2021-03-19
摘要： In accordance with an embodiment, a detection device includes: an infrared temperature sensor configured to provide a temperature signal associated with an heat emission of at least one individual within a monitored area; an electrostatic-charge-variation sensor configured to provide a charge-variation signal indicative of a variation of electrostatic charge associated with the at least one individual; and a processing unit, coupled to the infrared temperature sensor and to the electrostatic-charge-variation sensor, the processing unit configured to detect a presence of the at least one individual within the monitored area by receiving the temperature signal and the charge-variation signal, and jointly processing the temperature signal and charge.
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公开(公告)号：US11461257B2
公开(公告)日：2022-10-04
申请号：US17339083
申请日：2021-06-04
IPC分类号： G06F13/28 , G06F9/46 , G06F13/37 , G06F13/372 , G06F17/14
摘要： An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.
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公开(公告)号：US20220308615A1
公开(公告)日：2022-09-29
申请号：US17702362
申请日：2022-03-23
发明人： Barbaro MARANO , Mario CHIRICOSTA
摘要： A cell includes a first pair and a second pair of MOS transistors. Each of the first pair and second pair of MOS transistors have drain electrodes coupled to a respective common input node. Each of the first pair and second pair of MOS transistors includes a diode-connected MOS transistor and a latched MOS transistor. The latched MOS transistors of the first pair and second pair of MOS transistors have cross-coupled gate and drain electrodes. Source electrodes of the diode connected MOS transistors from the first pair and second pair of MOS transistors are coupled to a first current output common node to output a current to a first current collecting circuit. Source source electrodes of the latched MOS transistors of the first pair and second pair of MOS transistors are coupled to a second current output common node to output a current to a second current collecting circuit.
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公开(公告)号：US20220293498A1
公开(公告)日：2022-09-15
申请号：US17688013
申请日：2022-03-07
IPC分类号： H01L23/495 , H01L23/16 , H01L23/31 , H01L21/56
摘要： A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.
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公开(公告)号：US11442700B2
公开(公告)日：2022-09-13
申请号：US16833340
申请日：2020-03-27
摘要： A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.
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公开(公告)号：US11436162B2
公开(公告)日：2022-09-06
申请号：US16881949
申请日：2020-05-22
申请人： STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
发明人： Riccardo Gemelli , Denis Dutey , Om Ranjan
摘要： A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.
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公开(公告)号：US20220271740A1
公开(公告)日：2022-08-25
申请号：US17676005
申请日：2022-02-18
发明人： Marco VITI
摘要： A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.
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公开(公告)号：US20220269627A1
公开(公告)日：2022-08-25
申请号：US17673677
申请日：2022-02-16
IPC分类号： G06F13/362 , G06F1/12
摘要： In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. A selection line for each one of the slave devices couples the master device with a respective slave device and is dedicated to selection by the master device of the respective slave device for communication over the shared data communication bus. Each of the slave devices is able to send an interrupt request to the master device over the respective selection line to be served by the master device initiating a communication over the shared data communication bus, each selection line thereby being a bidirectional communication line between the respective slave device and the master device.
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89.发明申请公开(公告)号：US20220263509A1
公开(公告)日：2022-08-18
申请号：US17671844
申请日：2022-02-15
IPC分类号： H03K19/0175 , G06F13/12
摘要： A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.
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公开(公告)号：US20220263481A1
公开(公告)日：2022-08-18
申请号：US17665399
申请日：2022-02-04
IPC分类号： H03F3/45
摘要： A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.
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