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公开(公告)号：US20220375956A1
公开(公告)日：2022-11-24
申请号：US17772280
申请日：2020-11-13
发明人： Hitoshi KUNITAKE , Satoru OHSHITA , Kazuki TSUDA , Tatsuya ONUKI
IPC分类号： H01L27/11573 , H01L27/11582 , G11C16/08
摘要： A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.
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公开(公告)号：US20220375529A1
公开(公告)日：2022-11-24
申请号：US17772740
申请日：2020-10-16
IPC分类号： G11C16/26
摘要： A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.
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公开(公告)号：US20220375521A1
公开(公告)日：2022-11-24
申请号：US17773887
申请日：2020-11-09
IPC分类号： G11C14/00 , H01L27/11582
摘要： A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.
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公开(公告)号：US11510002B2
公开(公告)日：2022-11-22
申请号：US17260686
申请日：2019-08-23
发明人： Takayuki Ikeda , Kiyotaka Kimura , Takeya Hirose
IPC分类号： H04R3/00 , H01L27/105 , H01L27/12 , H01L29/786 , H04R1/40
摘要： A semiconductor device with a novel structure which can identify the sound source is provided. The semiconductor device includes a microphone array, delay circuits, and a signal processing circuit. The delay circuit includes a first selection circuit, which selects a microphone, signal retention circuits, which retain voltages depending on the sound signal, and a second selection circuit, which selects a signal retention circuit. Each signal retention circuit includes a transistor which includes a semiconductor layer including an oxide semiconductor in its channel formation region. The first selection circuit writes the voltage of discreet sound signals to the signal retention circuit. The second selection circuit selects at different timings the voltages which are retained in the signal retention circuit and generates the output signal corresponding to the delayed sound signal.
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公开(公告)号：US11508787B2
公开(公告)日：2022-11-22
申请号：US16867890
申请日：2020-05-06
发明人： Takuya Kawata , Akihiro Chida
摘要： A display device, an electronic device, or a lighting device that is unlikely to be broken is provided. A flexible first substrate and a flexible second substrate overlap with each other with a display element provided therebetween. A flexible third substrate is bonded on the outer surface of the first substrate, and a flexible fourth substrate is bonded on the outer surface of the second substrate. The third substrate is formed using a material softer than the first substrate, and the fourth substrate is formed using a material softer than the second substrate.
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公开(公告)号：US20220367723A1
公开(公告)日：2022-11-17
申请号：US17869960
申请日：2022-07-21
发明人： Junichi KOEZUKA , Yasutaka NAKAZAWA
IPC分类号： H01L29/786 , G01N23/223 , G01N23/2273 , H01L29/04
摘要： A semiconductor device with favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The first insulating layer is in contact with part of the top surface of the semiconductor layer, the conductive layer is positioned over the first insulating layer, and the second insulating layer is positioned over the semiconductor layer. The semiconductor layer contains a metal oxide and includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer. The second region is in contact with the second insulating layer. The second insulating layer contains oxygen and a first element. The first element is one or more of phosphorus, boron, magnesium, aluminum, and silicon.
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公开(公告)号：US20220366958A1
公开(公告)日：2022-11-17
申请号：US17618993
申请日：2020-06-09
发明人： Fumika AKASAWA , Munehiro KOZUMA
IPC分类号： G11C11/405 , H01L27/108 , H01L27/12 , H01L29/786
摘要： Since power source voltages are different depending on circuits used for devices, a circuit for outputting at least two or more power sources is additionally prepared. An object is to unify outputs of the power source voltages. A transistor using an oxide semiconductor is provided in such a manner that electrical charge is retained in a node where the transistor and a capacitor are electrically connected to each other, a reset signal is applied to a gate of the transistor to switch the states of the transistor from off to on, and the node is reset when the transistor is on. A circuit configuration that generates and utilizes a potential higher than or equal to a potential of a single power source can be achieved.
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公开(公告)号：US20220366845A1
公开(公告)日：2022-11-17
申请号：US17723613
申请日：2022-04-19
发明人： Hajime KIMURA , Takayuki IKEDA
IPC分类号： G09G3/3225
摘要： A semiconductor device includes first to tenth transistors and first to fourth capacitors. Gates of the first and the fourth transistors are electrically connected to each other. First terminals of the first, second, fifth, and eighth transistors are electrically connected to a first terminal of the fourth capacitor. A second terminal of the fifth transistor is electrically connected to a gate of the sixth transistor and a first terminal of the second capacitor. A second terminal of the eighth transistor is electrically connected to a gate of the ninth transistor and a first terminal of the third capacitor. Gates of the second, seventh, and tenth transistors are electrically connected to first terminals of the third and fourth transistors and a first terminal of the first capacitor. First terminals of the sixth and seventh transistors are electrically connected to a second terminal of the second capacitor.
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公开(公告)号：US11501728B2
公开(公告)日：2022-11-15
申请号：US17206746
申请日：2021-03-19
发明人： Hajime Kimura , Atsushi Umezaki
摘要： A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.
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公开(公告)号：US11501695B2
公开(公告)日：2022-11-15
申请号：US17271221
申请日：2019-09-03
IPC分类号： G09G3/32
摘要： The power consumption of a display device is reduced. The power consumption of a driver circuit in a display device is reduced. A pixel included in the display device includes a display element. The pixel is configured to have a function of retaining a first voltage corresponding to a first input pulse signal and a function of driving the display element with a third voltage obtained by addition of a second voltage corresponding to a second input pulse signal to the first voltage.
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