-
公开(公告)号：US20230055062A1
公开(公告)日：2023-02-23
申请号：US17796903
申请日：2021-02-08
发明人： Yuki OKAMOTO , Munehiro KOZUMA , Tatsuya ONUKI
IPC分类号： G06F7/544 , H01L27/108 , H01L27/12 , H01L29/786
摘要： A semiconductor device with a novel structure is provided. A plurality of memory circuits, a switching circuit, and an arithmetic circuit are included. Each of the plurality of memory circuits has a function of retaining weight data and a function of outputting the weight data to a first wiring. The switching circuit has a function of switching a conduction state between any one of the plurality of first wirings and a second wiring. The arithmetic circuit has a function of performing arithmetic processing using input data and the weight data supplied to the second wiring. The memory circuits are provided in a first layer. The switching circuit and the arithmetic circuit are provided in a second layer. The first layer is provided in a layer different from the second layer.
-
公开(公告)号：US20220375956A1
公开(公告)日：2022-11-24
申请号：US17772280
申请日：2020-11-13
发明人： Hitoshi KUNITAKE , Satoru OHSHITA , Kazuki TSUDA , Tatsuya ONUKI
IPC分类号： H01L27/11573 , H01L27/11582 , G11C16/08
摘要： A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.
-
公开(公告)号：US20210384355A1
公开(公告)日：2021-12-09
申请号：US17284553
申请日：2019-10-15
发明人： Eri SATO , Tatsuya ONUKI , Yuto YAKUBO , Hitoshi KUNITAKI
IPC分类号： H01L29/786 , H01L29/24
摘要： A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.
-
公开(公告)号：US20210183860A1
公开(公告)日：2021-06-17
申请号：US17047143
申请日：2019-04-11
IPC分类号： H01L27/105 , H01L27/12 , H01L29/24 , H01L29/786
摘要： A novel semiconductor device is provided. A semiconductor device includes a plurality of cell arrays and a plurality of peripheral circuits. The cell array includes a plurality of memory cells. The peripheral circuit includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit. The first driver circuit and the second driver circuit each have a function of supplying a selection signal to the cell array. The first amplifier circuit and the second amplifier circuit each have a function of amplifying a potential input from the cell array. The third amplifier circuit and the fourth amplifier circuit each have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit. The first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit have a region overlapping with the cell array. A transistor included in the memory cell includes a metal oxide in a channel formation region.
-
公开(公告)号：US20210124578A1
公开(公告)日：2021-04-29
申请号：US17074872
申请日：2020-10-20
发明人： Shunpei YAMAZAKI , Hajime KIMURA , Tatsuya ONUKI
IPC分类号： G06F9/30 , G11C11/4093 , G11C11/402 , G11C11/408 , G11C11/4094
摘要： To provide a data processing system that includes a nonvolatile memory device capable of storing multilevel data and enables increasing storage capacity of a main memory device when the data processing system is activated. The data processing system includes an arithmetic processing device, a main memory device, and a nonvolatile memory device. The main memory device includes a volatile memory device, and the nonvolatile memory device is configured to store multilevel data in one memory cell. When the data processing system is deactivated, the nonvolatile memory device stores binary data, whereby the stored data can be held for a long time. Upon activation, the nonvolatile memory device stores multilevel data, whereby increasing storage capacity. When the storage capacity is increased, a free space is generated in the nonvolatile memory device, which can be used as a part of the main memory device of the data processing system.
-
公开(公告)号：US20210081023A1
公开(公告)日：2021-03-18
申请号：US17104460
申请日：2020-11-25
发明人： Shuhei MAEDA , Shuhei NAGATSUKA , Tatsuya ONUKI , Kiyoshi KATO
IPC分类号： G06F1/3234 , G11C16/30 , G11C14/00 , G11C5/14
摘要： To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.
-
公开(公告)号：US20210027828A1
公开(公告)日：2021-01-28
申请号：US17041037
申请日：2019-03-20
发明人： Shunpei YAMAZAKI , Kiyoshi KATO , Takahiko ISHIZU , Tatsuya ONUKI
IPC分类号： G11C11/408 , H01L27/105 , H01L27/12 , H01L29/24 , H01L29/786
摘要： A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.
-
公开(公告)号：US20200373302A1
公开(公告)日：2020-11-26
申请号：US16767645
申请日：2018-11-30
IPC分类号： H01L27/105 , H01L27/12 , H01L29/786
摘要： A novel semiconductor device is provided. A back gate voltage of a transistor including a gate and a back gate is adjusted based on the operating temperature. The operating temperature is acquired by a temperature detector circuit. The temperature detection circuit outputs the temperature information as a digital signal. The digital signal is input to a voltage control circuit. The voltage control circuit outputs a first voltage corresponding to the digital signal. The back gate voltage is determined by a voltage in which a first voltage is added to a reference voltage.
-
公开(公告)号：US20200279589A1
公开(公告)日：2020-09-03
申请号：US16643755
申请日：2018-09-03
摘要： To provide a novel semiconductor device.The semiconductor device includes cell arrays and peripheral circuits; the cell arrays include memory cells; the peripheral circuits includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit; the first driver circuit and the second driver circuit have a function of supplying a selection signal to the cell array; the first amplifier circuit and the second amplifier circuit have a function of amplifying a potential input from the cell array; the third amplifier circuit and the fourth amplifier circuit have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit; the first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit include a region overlapping with the cell array; and the memory cells include a metal oxide in a channel formation region.
-
公开(公告)号：US20190377401A1
公开(公告)日：2019-12-12
申请号：US16476642
申请日：2018-01-09
发明人： Shuhei MAEDA , Shuhei NAGATSUKA , Tatsuya ONUKI , Kiyoshi KATO
IPC分类号： G06F1/3234 , G11C5/14 , G11C16/30 , G11C14/00
摘要： To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.
-
-
-
-
-
-
-
-
-
搜索结果
98 条记录 (耗时 0.03 秒)