公开(公告)号：US07898836B2

公开(公告)日：2011-03-01

申请号：US12106927

申请日：2008-04-21

申请人： Thomas Kuenemund ,  Karl Zapf ,  Artur Wroblewski

发明人： Thomas Kuenemund ,  Karl Zapf ,  Artur Wroblewski

IPC分类号： G11C17/00

CPC分类号： G11C17/12 ,  G11C17/18

摘要： An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.

摘要翻译： 一种掩蔽存储单元的阵列，包括第一列中的第一存储单元和第二不同列中的第二存储单元，其中第一存储单元能够被访问，以便根据第一二进制掩码信号输出， 在第一输出处的第一二进制值和第二输出处的第二二进制值，反之亦然，其中第二存储器单元能够被访问，以便根据第二二进制掩码信号输出第二二进制值 第三输出和第二二进制值在第四输出或反之亦然，并且其中存储器单元的第二和第三输出连接到存储器阵列的相同位线。

公开(公告)号：US20110032742A1

公开(公告)日：2011-02-10

申请号：US12462732

申请日：2009-08-07

申请人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

发明人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/115

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

公开(公告)号：US20110026354A1

公开(公告)日：2011-02-03

申请号：US12784025

申请日：2010-05-20

申请人： Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu ,  Jiann-Tseng Huang ,  We-Li Liao

发明人： Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu ,  Jiann-Tseng Huang ,  We-Li Liao

IPC分类号： G11C5/14 ,  G11C8/00 ,  G11C17/00

CPC分类号： G11C8/12 ,  G11C17/18

摘要： An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.

摘要翻译： OTP存储器阵列包括耦合到多个存储体的位线。 每个存储体包括多个存储单元，一个页脚和一个偏置装置，并与一个电流镜相关联。 当存储器单元被激活（例如，用于读取）时，包括激活的存储器单元的存储体被称为激活的存储体，并且其他存储体被称为去激活存储体。 电流跟踪装置用于补偿激活的存储体中的去激活的存储器单元中的位线泄漏电流。 此外，禁用存储器组和相关联的电流镜中的脚和偏置器件被配置为通过去激活的存储体中的去激活的存储器单元来减少/消除位线电流泄漏。

公开(公告)号：US20110019459A1

公开(公告)日：2011-01-27

申请号：US12883172

申请日：2010-09-15

申请人： Guobiao Zhang

发明人： Guobiao Zhang

IPC分类号： G11C17/00

CPC分类号： H01L21/8221 ,  G11C17/10 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11253 ,  H01L2224/32145 ,  H01L2224/48147 ,  H01L2224/73265

摘要： The present invention discloses a three-dimensional mask-programmable read-only memory with reserved space (3D-MPROMRS). It is released in a sequence of versions. In the original version, its storage space comprises an initial-release space and a reserved space. The initial-release space stores the multimedia files from the initial release. The reserved space, although large enough to store at least one multimedia file, does not store any file. In the later version, the reserved space stores the new release.

摘要翻译： 本发明公开了一种具有预留空间（3D-MPROMRS）的三维掩模可编程只读存储器。 它以一系列版本发布。 在原始版本中，其存储空间包括初始释放空间和预留空间。 初始版本存储从初始版本的多媒体文件。 保留的空间虽然足够大以至少存储一个多媒体文件，但并不存储任何文件。 在后期版本中，预留空间存储新版本。

公开(公告)号：US07869251B2

公开(公告)日：2011-01-11

申请号：US12239469

申请日：2008-09-26

申请人： Ramnath Venkatraman ,  Ruggero Castagnetti ,  Subramanian Ramesh

发明人： Ramnath Venkatraman ,  Ruggero Castagnetti ,  Subramanian Ramesh

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state.

摘要翻译： 公开了一种用于提供基于SRAM存储器技术的快速响应一次可编程（OTP）存储器和MOS晶体管的固有击穿特性的方法和装置。 SRAM存储单元电路的每个存储单元连接到编程电路。 编程电路由连接到SRAM存储器电路的两个交叉耦合反相器的存储节点（SN和SNB，其中SNB是SN的互补值）的两组MOS晶体管组成。 将期望的数据组加载到电路中，然后通过施加并重复地循环编程电路的MOS晶体管的源极和漏极上的“老化”电压并接近特性的ON状态触发电压而被烧录 双极结晶体管包含在MOS晶体管内。 在重复循环源极至漏极电压之后，编程电路内的目标MOS晶体管在晶体管的栅极，漏极和/或源极之间分解和短路。 当系统恢复正常运行时，编程电路将连接到地，Vdd或Vss，SRAM单元电路的两个节点之一将通过编程电路短路到地Vdd或Vss，从而强制 保留编程数据状态。

公开(公告)号：US07852660B2

公开(公告)日：2010-12-14

申请号：US12425856

申请日：2009-04-17

申请人： Wenzhong Zhu ,  Hai Li ,  Yiran Chen ,  Xiaobin Wang ,  Henry Huang ,  Haiwen Xi

发明人： Wenzhong Zhu ,  Hai Li ,  Yiran Chen ,  Xiaobin Wang ,  Henry Huang ,  Haiwen Xi

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C17/00

CPC分类号： G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

摘要： An apparatus and method for enhancing read and write sense margin in a memory cell having a resistive sense element (RSE), such as but not limited to a resistive random access memory (RRAM) element or a spin-torque transfer random access memory (STRAM) element. The RSE has a hard programming direction and an easy programming direction. A write current is applied in either the hard programming direction or the easy programming direction to set the RSE to a selected programmed state. A read circuit subsequently passes a read sense current through the cell in the hard programming direction to sense the selected programmed state of the cell.

摘要翻译： 一种用于增强具有电阻感测元件（RSE）的存储单元中的读和写检测余量的装置和方法，所述电阻感测元件（RSE）例如但不限于电阻随机存取存储器（RRAM）元件或自旋转矩传递随机存取存储器 ）元素。 RSE具有硬编程方向和简单的编程方向。 写入电流应用在硬编程方向或简易编程方向上，以将RSE设置为选定的编程状态。 读取电路随后在硬编程方向上传递通过单元的读取感测电流以感测所选择的单元的编程状态。

公开(公告)号：US07852656B2

公开(公告)日：2010-12-14

申请号：US12071127

申请日：2008-02-15

申请人： Chang-Hee Shin ,  Ki-Seok Cho

发明人： Chang-Hee Shin ,  Ki-Seok Cho

IPC分类号： G11C17/00

CPC分类号： G11C17/18

摘要： One-time programmable cell and memory device having the same includes a first metal oxide semiconductor (MOS) transistor configured to form a current path between a first node and a second node in response to a read-control signal, a second MOS transistor configured to form a current path between a third node and the second node in response to a write-control signal and an anti-fuse connected between the second node and a ground voltage terminal, wherein a voltage applied to the second node is output as an output signal.

摘要翻译： 其一次性可编程单元和存储器件包括：第一金属氧化物半导体（MOS）晶体管，被配置为响应于读取控制信号在第一节点和第二节点之间形成电流路径，第二MOS晶体管被配置为 响应于写入控制信号和连接在第二节点和地电压端子之间的反熔丝形成第三节点和第二节点之间的电流路径，其中施加到第二节点的电压作为输出信号输出 。

公开(公告)号：US20100272265A1

公开(公告)日：2010-10-28

申请号：US12832774

申请日：2010-07-08

申请人： Sebastian Ahmed

发明人： Sebastian Ahmed

IPC分类号： G06F12/00 ,  G11C17/00 ,  H04L9/00

CPC分类号： G11C17/18

摘要： Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

摘要翻译： 公开了一种控制一次可编程（OTP）存储器的系统和方法。 一种方法可以包括确定集成电路中的硬件能力总线的功能。 该方法还可以包括基于功能将数据存储在集成电路的第一寄存器中。 该方法还可以包括通过基于该数据在集成电路中设置一次可编程存储体中的至少一个位来禁用集成电路中的功能。

公开(公告)号：US20100214816A1

公开(公告)日：2010-08-26

申请号：US12652272

申请日：2010-01-05

申请人： Hyunsu Choi ,  Jung-Hak Song ,  Jungmin Choi

发明人： Hyunsu Choi ,  Jung-Hak Song ,  Jungmin Choi

IPC分类号： G11C17/00 ,  G11C17/16 ,  G11C7/00

CPC分类号： G11C7/1036 ,  G11C17/18

摘要： Semiconductor devices include a plurality of fuses and a plurality of program circuits, respective ones of which are configured to program respective ones of the plurality of fuses. The devices further include a shift register configured to activate at least two of the program circuits. In some embodiments, the shift register includes a first shift register configured to generate first select signals and a second shift register configured to generate second select signals corresponding to data to be programmed to the plurality of fuses. Respective ones of the program circuits may be configured to program respective ones of the fuses responsive to respective pairs of the first select signals and the second select signals.

摘要翻译： 半导体器件包括多个保险丝和多个编程电路，其中各个被配置为对多个保险丝中的相应的保险丝进行编程。 该装置还包括配置成激活至少两个编程电路的移位寄存器。 在一些实施例中，移位寄存器包括被配置为产生第一选择信号的第一移位寄存器和被配置为产生对应于要编程到多个保险丝的数据的第二选择信号的第二移位寄存器。 各个程序电路可以被配置为响应于第一选择信号和第二选择信号的相应对而对各个熔丝进行编程。

公开(公告)号：US07783429B2

公开(公告)日：2010-08-24

申请号：US11060591

申请日：2005-02-18

申请人： Peter Walden ,  Rodion Demine

发明人： Peter Walden ,  Rodion Demine

IPC分类号： G06F19/00 ,  G11C17/00 ,  H01J49/26

CPC分类号： G01N33/6848

摘要： The invention relates to a method of peptide sequencing from peptide fragment mass data, wherein a plurality of candidate peptide sequences are determined comprises the steps of: calculating peptide fragment masses, searching a plurality of peak data for masses matching said calculated peptide fragment masses, annotating all permutations of said peak data with amino acid sequences that correspond to the calculated peptide fragment masses, extending said potential sequences to resulting masses with additional matching masses, extending stepwise additions until the resulting masses correspond to parental peptide masses or said parental peptide masses minus the mass of water, and identifying at least one peptide sequence by deleting sequences that can not be extended to endpoints of said parental peptide masses, and deleting identical sequences generated.

摘要翻译： 本发明涉及从肽片段质量数据进行肽测序的方法，其中确定多个候选肽序列包括以下步骤：计算肽片段质量，搜索多个峰数据以获得与所计算的肽片段质量匹配的质量，注释 所述峰数据与所计算的肽片段质量对应的氨基酸序列的所有排列，将所述潜在序列扩展到具有附加匹配质量的所得质量，延伸逐步添加，直到所得质量对应于亲本肽质量或所述亲本肽质量减去 并且通过删除不能扩展到所述亲本肽质量的端点的序列以及删除产生的相同序列来鉴定至少一个肽序列。