公开(公告)号：US08411399B2

公开(公告)日：2013-04-02

申请号：US12839148

申请日：2010-07-19

申请人： Ramnath Venkatraman ,  Ruggero Castagnetti

发明人： Ramnath Venkatraman ,  Ruggero Castagnetti

IPC分类号： H02H3/22

CPC分类号： H01L27/0629 ,  H01L27/0805 ,  H03H7/004 ,  Y10T29/413

摘要： An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.

摘要翻译： 集成电路电源去耦电路包括电容器和保护电路。 电容器具有第一端子和第二端子。 保护电路包括具有第一导电路径的第一晶体管和具有第二导电路径的第二晶体管。 第一导电路径的一个端子连接到电容器的第一端子，并且第一导电路径的另一个端子连接到第一电源轨道。 第二导电路径的一个端子连接到电容器的第二端子，第二导电路径的另一个端子连接到第二电源轨道。

公开(公告)号：US20130057338A1

公开(公告)日：2013-03-07

申请号：US13226038

申请日：2011-09-06

申请人： Ramnath Venkatraman ,  Shashidhara S. Bapat ,  Ruggero Castagnetti

发明人： Ramnath Venkatraman ,  Shashidhara S. Bapat ,  Ruggero Castagnetti

IPC分类号： H01L25/065

CPC分类号： H03K19/0016

摘要： A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.

摘要翻译： 冲击电流控制器包括连接的时钟模块，以基于对与输入的睡眠控制信号相对应的预设数量的时钟周期计数来提供延迟的睡眠控制信号。 此外，引入电流控制器包括环形振荡器模块，其连接以基于对应于虚拟电源线电压的预设数量的环形振荡器周期来计数延迟的睡眠控制信号。 一种控制加速电流的方法包括：基于对与输入的睡眠控制信号相对应的预设数量的时钟周期进行计数，提供延迟睡眠控制信号，并且基于对预定数量的环形振荡器周期进行计数来保持延迟的睡眠控制信号 到虚拟电源线电压。

公开(公告)号：US20120290994A1

公开(公告)日：2012-11-15

申请号：US13103461

申请日：2011-05-09

申请人： Benjamin Mbouombouo ,  Ramnath Venkatraman ,  Ruggero Castagnetti

发明人： Benjamin Mbouombouo ,  Ramnath Venkatraman ,  Ruggero Castagnetti

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/505 ,  G06F2217/78

摘要： A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.

摘要翻译： 减少逻辑单元的总功耗的方法包括：选择对应于至少一个路径的逻辑单元的分布，在逻辑单元的分布中计算每个逻辑单元的动态到静态功率比，并将动态到静态功率比排列 每个逻辑单元分成下组，中间组和上组逻辑单元。 此外，该方法包括交换逻辑单元的下组和用于重构的中间组逻辑单元的逻辑单元的上组，并验证重构的中间组逻辑单元的路径定时。 还提供了使用布尔方程和逻辑单元组来降低总功耗的方法。

公开(公告)号：US20110051304A1

公开(公告)日：2011-03-03

申请号：US12839148

申请日：2010-07-19

申请人： Ramnath Venkatraman ,  Ruggero Castagnetti

发明人： Ramnath Venkatraman ,  Ruggero Castagnetti

IPC分类号： H02H9/02 ,  H03H7/00 ,  H01L21/00

CPC分类号： H01L27/0629 ,  H01L27/0805 ,  H03H7/004 ,  Y10T29/413

摘要： An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.

摘要翻译： 集成电路电源去耦电路包括电容器和保护电路。 电容器具有第一端子和第二端子。 保护电路包括具有第一导电路径的第一晶体管和具有第二导电路径的第二晶体管。 第一导电路径的一个端子连接到电容器的第一端子，并且第一导电路径的另一个端子连接到第一电源轨道。 第二导电路径的一个端子连接到电容器的第二端子，第二导电路径的另一个端子连接到第二电源轨道。

公开(公告)号：US20050047238A1

公开(公告)日：2005-03-03

申请号：US10655053

申请日：2003-09-03

申请人： Ruggero Castagnetti ,  Ramnath Venkatraman ,  Subramanian Ramesh

发明人： Ruggero Castagnetti ,  Ramnath Venkatraman ,  Subramanian Ramesh

IPC分类号： G11C5/02 ,  G11C7/02 ,  H01L27/02 ,  H01L27/105

CPC分类号： G11C5/025 ,  H01L27/0203 ,  H01L27/105

摘要： A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.

公开(公告)号：US06806551B2

公开(公告)日：2004-10-19

申请号：US10376401

申请日：2003-02-28

申请人： Yauh-Ching Liu ,  Ruggero Castagnetti ,  Ramnath Venkatraman

发明人： Yauh-Ching Liu ,  Ruggero Castagnetti ,  Ramnath Venkatraman

IPC分类号： H01L2900

CPC分类号： H01L23/5258 ,  H01L23/5329 ,  H01L2224/05022 ,  H01L2924/01019

摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.

摘要翻译： 保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。 电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。 导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。 然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

公开(公告)号：US06687114B1

公开(公告)日：2004-02-03

申请号：US10403433

申请日：2003-03-31

申请人： Arvind Kamath ,  Ruggero Castagnetti

发明人： Arvind Kamath ,  Ruggero Castagnetti

IPC分类号： H01G4228

CPC分类号： H01L27/1087 ,  H01L27/10894 ,  H01L29/66181

摘要： A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.

摘要翻译： 具有在硅衬底中形成的晶体管和电容器的存储单元。 电容器形成有在硅衬底的投影表面区域中蚀刻的下导电板。 下导电板具有至少一个vee形状的横截面，其中，vee的侧面与硅衬底的顶表面成约五十五度的角度。 下导电板的表面积比其中蚀刻下导电板的硅衬底的投影表面积大约百分之七点三。 电容器介电层由邻近下导电板设置的第一沉积介电层形成。 顶部导电板设置在电容器电介质层附近并与下部导电板相对。 晶体管形成为具有由沟道区域分离的源极和漏极区域以及由第一沉积介电层形成的栅极电介质层。

公开(公告)号：US06566171B1

公开(公告)日：2003-05-20

申请号：US09882404

申请日：2001-06-12

申请人： Yauh-Ching Liu ,  Ruggero Castagnetti ,  Ramnath Venkatraman

发明人： Yauh-Ching Liu ,  Ruggero Castagnetti ,  Ramnath Venkatraman

IPC分类号： H01L2182

CPC分类号： H01L23/5258 ,  H01L23/5329 ,  H01L2224/05022 ,  H01L2924/01019

摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.

摘要翻译： 保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。 电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。 导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。 然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

公开(公告)号：US20130166931A1

公开(公告)日：2013-06-27

申请号：US13336826

申请日：2011-12-23

申请人： Ruggero Castagnetti ,  Ting Zhou ,  Ramnath Venkatraman

发明人： Ruggero Castagnetti ,  Ting Zhou ,  Ramnath Venkatraman

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/22 ,  G11C11/4074 ,  G11C2207/2227 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Described embodiments provide for a memory system which power-gates a memory operating at a first clock. Control logic in the memory system activates, during a rising edge of a second clock, the memory from a sleep mode. The memory is accessed. After a cycle of the first clock, the control logic asserts a power-gating signal, thereby returning the memory to the sleep mode. The frequency of the second clock is less than a frequency of the first clock.

摘要翻译： 所描述的实施例提供对在第一时钟操作的存储器进行供电的存储器系统。 存储器系统中的控制逻辑在第二时钟的上升沿期间将存储器从睡眠模式激活。 内存被访问。 在第一时钟的周期之后，控制逻辑断言电源门控信号，从而将存储器返回到睡眠模式。 第二时钟的频率小于第一时钟的频率。

公开(公告)号：US08112734B2

公开(公告)日：2012-02-07

申请号：US12240210

申请日：2008-09-29

申请人： Benjamin Mbouombouo ,  Ramnath Venkatraman ,  Ruggero Castagnetti

发明人： Benjamin Mbouombouo ,  Ramnath Venkatraman ,  Ruggero Castagnetti

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5068

摘要： A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit design, (C) generating an adaptive body biasing mesh and (D) generating a layout of the integrated circuit design based upon a plurality of adaptive body biasing corners.

摘要翻译： 将自适应主体偏置结合到集成电路设计流程中的方法包括以下步骤：（A）在集成电路设计流程的接合布局阶段期间增加自适应主体偏置输入/输出（I / O），（B）布局规划集成电路 （C）产生自适应主体偏置网格和（D）基于多个自适应主体偏置角产生集成电路设计的布局。