公开(公告)号：US09543238B1

公开(公告)日：2017-01-10

申请号：US14808766

申请日：2015-07-24

Applicant: Fitipower Integrated Technology, Inc.

Inventor： Shang-Cheng Yu ,  Chih-Nan Cheng

IPC: H01L23/495

CPC classification number: H01L23/49541 ,  H01L23/495 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device includes a center semiconductor chip with a plurality of die pads, a plurality of lead frames, and a plurality of connecting components. The lead frame encapsulates the center semiconductor chip. Each connecting components establishes an electrical connection between the center semiconductor chip and the lead frame. At least one of the center semiconductor chip, the lead frame, and the connecting component forms an indicator.

Abstract translation: 半导体器件包括具有多个管芯焊盘的中心半导体芯片，多个引线框架和多个连接部件。 引线框封装中心半导体芯片。 每个连接部件在中心半导体芯片和引线框架之间建立电连接。 中心半导体芯片，引线框架和连接部件中的至少一个形成指示器。

公开(公告)号：US09276060B2

公开(公告)日：2016-03-01

申请号：US14497778

申请日：2014-09-26

Applicant: Fitipower Integrated Technology, Inc.

Inventor： Chih-Nan Cheng

IPC: H01L29/74 ,  H01L29/06 ,  H01L29/73 ,  H01L29/747

CPC classification number: H01L29/0607 ,  H01L29/7302 ,  H01L29/747

Abstract: A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region via at least one conducting channel.

Abstract translation: 三极管包括半导体，深n阱，p阱，n +掺杂区和掺杂区。 深n阱邻近半导体衬底设置。 p阱包含在深n阱中，并用作三极管的集电极区域。 n +掺杂区域用作三极管的基极区域。 p +掺杂区域用作三极管的发射极区域。 深n阱经由至少一个导电沟道耦合到n +掺杂区域。

公开(公告)号：US20140354678A1

公开(公告)日：2014-12-04

申请号：US14140578

申请日：2013-12-26

Applicant: Fitipower Integrated Technology, Inc.

Inventor： CHONG-XING WANG

IPC: G09G5/02

CPC classification number: G09G5/02 ,  G09G2320/0606 ,  G09G2320/0666 ,  G09G2320/08 ,  G09G2330/021

Abstract: A display control method of a display device having a color engine. A mode setting interface is started which comprises an option for setting a working status of the color engine. When the option is operated, the color engine setting interface is started. A working status of the color engine is set via the color engine setting interface. When the color engine is in an active status, the color engine is controlled to process content to be displayed.

Abstract translation: 具有彩色引擎的显示装置的显示控制方法。 启动模式设置界面，其包括用于设置彩色引擎的工作状态的选项。 当操作该选项时，启动彩色引擎设置界面。 彩色引擎的工作状态通过颜色引擎设置界面进行设置。 当彩色引擎处于活动状态时，颜色引擎被控制以处理要显示的内容。

公开(公告)号：US20140184574A1

公开(公告)日：2014-07-03

申请号：US14140563

申请日：2013-12-26

Applicant: FITIPOWER INTEGRATED TECHNOLOGY, INC.

Inventor： WEN-SHIAN SHIE ,  TUNG-SHUAN CHENG

IPC: G09G5/18

CPC classification number: G09G5/008 ,  G09G3/3611 ,  G09G3/3688 ,  G09G2330/06 ,  G09G2370/08

Abstract: A display device includes a timing control circuit and a data driving circuit. The data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The data driving circuit also receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from a frequency of the second clock signal.

Abstract translation: 显示装置包括定时控制电路和数据驱动电路。 数据驱动电路从定时控制电路接收第一时钟嵌入式训练数据，执行第一时钟训练，将数据驱动电路的工作频率调整为等于第一时钟信号的频率，并接收第一时钟嵌入 来自定时控制电路的图像数据。 数据驱动电路还从定时控制电路接收第二时钟嵌入的训练数据，执行第二时钟训练以将数据驱动电路的工作频率调整为等于第二时钟信号的频率，并接收第二时钟 来自定时控制电路的嵌入图像数据。 第一时钟信号的频率与第二时钟信号的频率不同。

公开(公告)号：US20130162612A1

公开(公告)日：2013-06-27

申请号：US13716395

申请日：2012-12-17

Applicant: Fitipower Integrated Technology, Inc.

Inventor： MENG-WEI CHUANG

IPC: G09G3/28

CPC classification number: G09G3/28 ,  G09G3/34 ,  G09G3/344 ,  G09G3/3648 ,  G09G2300/0452 ,  G09G2300/08

Abstract: An electronic device includes a first display unit for displaying static images, a second display unit for displaying dynamic images, a gate driver connected to the first display unit and the second display unit; a source driver connected to the first display unit and the second display unit; a storage unit for storing visual content; and a processor. The processor is operative to determine at least one feature of the visual content; and control the gate driver and the source driver to selectively enable at least one of the first display unit and the second display unit, based on the at least one determined feature, to display the visual content.

Abstract translation: 电子设备包括用于显示静态图像的第一显示单元，用于显示动态图像的第二显示单元，连接到第一显示单元和第二显示单元的门驱动器; 连接到第一显示单元和第二显示单元的源极驱动器; 用于存储视觉内容的存储单元; 和处理器。 处理器可操作以确定视觉内容的至少一个特征; 并且基于所述至少一个确定的特征来控制所述栅极驱动器和所述源极驱动器以选择性地使所述第一显示单元和所述第二显示单元中的至少一个显示所述视觉内容。

公开(公告)号：US20130083437A1

公开(公告)日：2013-04-04

申请号：US13534034

申请日：2012-06-27

Applicant: CHING-HUA HUANG

Inventor： CHING-HUA HUANG

IPC: H02H9/04

CPC classification number: H01L27/0285 ,  H02H9/046

Abstract: An ESD elimination device includes an ESD elimination circuit connected between a power line and a ground line and an ESD detection circuit. The ESD detection circuit includes a switch unit and a resistor, the switch unit and the resistor are electrically connected between the power line and the ground line. The switch unit is turned on when an ESD event occurs in the power line, a detecting voltage is generated across the resistor when the switch unit is turned on, the detecting voltage is used for triggering the ESD elimination circuit to eliminate the ESD surge current caused by the ESD event.

Abstract translation: ESD消除装置包括连接在电力线和接地线之间的ESD消除电路以及ESD检测电路。 ESD检测电路包括开关单元和电阻器，开关单元和电阻器电连接在电力线和接地线之间。 当电源线发生ESD事件时，开关单元导通，当开关单元接通时，电阻器上产生检测电压，检测电压用于触发ESD消除电路，以消除ESD浪涌电流 通过ESD事件。

公开(公告)号：US20120038599A1

公开(公告)日：2012-02-16

申请号：US13175850

申请日：2011-07-02

Applicant: CHENG-LIN SHIU ,  JING-YUAN ZHENG

Inventor： CHENG-LIN SHIU ,  JING-YUAN ZHENG

IPC: G09G5/00

CPC classification number: G09G3/3688 ,  G09G2310/0248 ,  G09G2330/023 ,  G09G2330/04

Abstract: A source driver includes a first output buffer, a second output buffer, a first output switch, a second output switch, a third output switch, a fourth output switch, a first resistor, a second resistor, a third resistor, a fourth resistor, a first charge-sharing switch. The first and the second output buffer respectively enhances a first and a second pixel signal and respectively outputs a first and a second enhanced pixel signal to a display panel. The first output switch and the first resistor connected in series and the second output switch and the second resistor connected in series are connected in parallel between the first output buffer and the display panel. The third output switch and the third resistor connected in series and the fourth output switch and the fourth resistor connected in series are connected in parallel between the second output buffer and the display panel.

Abstract translation: 源极驱动器包括第一输出缓冲器，第二输出缓冲器，第一输出开关，第二输出开关，第三输出开关，第四输出开关，第一电阻器，第二电阻器，第三电阻器，第四电阻器， 第一个电荷共享开关。 第一和第二输出缓冲器分别增强第一和第二像素信号，并且分别将第一和第二增强像素信号输出到显示面板。 串联连接的第一输出开关和第一电阻器以及串联连接的第二输出开关和第二电阻并联连接在第一输出缓冲器和显示面板之间。 串联连接的第三输出开关和第三电阻器以及串联连接的第四输出开关和第四电阻并联连接在第二输出缓冲器和显示面板之间。

公开(公告)号：US07746017B2

公开(公告)日：2010-06-29

申请号：US12104664

申请日：2008-04-17

Applicant: Kai-Ping Lin ,  Tsung-Jen Lin

Inventor： Kai-Ping Lin ,  Tsung-Jen Lin

IPC: H02P1/00

CPC classification number: H02P7/04

Abstract: An exemplary fan driving system includes a driving device and a MOSFET group. The driving device includes a first adjustable resistor connected between its first voltage signal input terminal and ground, and a second adjustable resistor connected between its second voltage signal input terminal and ground. The MOSFET group includes two N-type MOSFETs and two P-type MOSFETs. The first terminal of the fan is connected to an anode of D1 and a cathode of D3. The second terminal of the fan is connected to an anode of D2 and a cathode of D4. Cathodes of the D1 and D2 are configured to connect a supply voltage. Anodes of the D3 and D4 both are grounded. The fan driving system can effectively discharge off the residual current in the coil of the fan at the moment of the MOSFET group being switched off.

Abstract translation: 示例性的风扇驱动系统包括驱动装置和MOSFET组。 所述驱动装置包括连接在其第一电压信号输入端和地之间的第一可调电阻器和连接在其第二电压信号输入端和地之间的第二可调电阻器。 MOSFET组包括两个N型MOSFET和两个P型MOSFET。 风扇的第一端子连接到D1的阳极和D3的阴极。 风扇的第二端子连接到D2的阳极和D4的阴极。 D1和D2的阴极配置为连接电源电压。 D3和D4的阳极都接地。 风扇驱动系统可以在MOSFET组关闭时有效地消除风扇线圈中的剩余电流。

公开(公告)号：US07586340B2

公开(公告)日：2009-09-08

申请号：US11733165

申请日：2007-04-09

Applicant: Kai-Ping Lin ,  Kai-Chi Lin ,  Tsung-Jen Lin

Inventor： Kai-Ping Lin ,  Kai-Chi Lin ,  Tsung-Jen Lin

IPC: H03B1/00 ,  H03K3/00

CPC classification number: H03K3/64

Abstract: An exemplary driving apparatus capable of generating a driving current, including: an analog input generating circuit, an analog input driving circuit, and an output circuit. The analog input generating circuit is electrically connected between a first voltage source and the ground and configured (i.e., structured and arranged) for supplying an adjustable analog signal. The analog input driving circuit is electrically connected between a second voltage source and the ground and configured for converting the analog signal into a pulsed signal. The output circuit is configured for converting the pulsed signal into a driving current as an output. The frequency of the pulsed signal can be adjusted via adjusting the analog signal and thereby varying the driving current. Thus the driving current can be adapted for the different target loads.

Abstract translation: 一种能够产生驱动电流的示例性驱动装置，包括：模拟输入产生电路，模拟输入驱动电路和输出电路。 模拟输入发生电路电连接在第一电压源和地之间并被配置（即，构造和布置），用于提供可调模拟信号。 模拟输入驱动电路电连接在第二电压源和地之间并被配置为将模拟信号转换为脉冲信号。 输出电路被配置为将脉冲信号转换为作为输出的驱动电流。 脉冲信号的频率可以通过调节模拟信号进行调整，从而改变驱动电流。 因此，驱动电流可以适应不同的目标负载。

公开(公告)号：US20090096022A1

公开(公告)日：2009-04-16

申请号：US12133388

申请日：2008-06-05

Applicant: CHYH-YIH CHANG ,  HSING-HUA SUN ,  TSUAN-LUN LUNG ,  CHEN-MING CHIU

Inventor： CHYH-YIH CHANG ,  HSING-HUA SUN ,  TSUAN-LUN LUNG ,  CHEN-MING CHIU

IPC: H01L29/78

CPC classification number: H01L29/7817 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095

Abstract: An exemplary lateral diffused metal oxide semiconductor device includes a first-type substrate, a gate oxide film disposed on the first-type substrate, a poly gate disposed on the gate oxide film, a first second-type slightly doped region formed in the first-type substrate and acting as a well, a first first-type highly doped region formed in the well and acting as a body, a first second-type highly doped region formed in the body and acting as a source, a second second-type highly doped region formed in the well and acting as a drain, a second first-type highly doped region formed in the body, and a first fist-type doped region formed in the body and is beneath the source.

Abstract translation: 示例性的横向扩散金属氧化物半导体器件包括第一类型衬底，设置在第一类型衬底上的栅极氧化膜，设置在栅极氧化物膜上的多晶硅栅极，形成在第一衬底中的第一第二类型轻掺杂区域， 形成在阱中并用作体的第一第一第一高掺杂区域，形成在体内并作为源的第一第二第二类型高掺杂区域，第二第二高度掺杂区域 掺杂区域形成在阱中并用作漏极，形成在体内的第二第一第一高掺杂区域和形成在体内并位于源极之下的第一第一掺杂区域。