公开(公告)号：US20100168873A1

公开(公告)日：2010-07-01

申请号：US12644961

申请日：2009-12-22

Applicant: Ales LOIDL ,  Ignazio Bellomo ,  Luca Giussani ,  David Vincenzoni

Inventor： Ales LOIDL ,  Ignazio Bellomo ,  Luca Giussani ,  David Vincenzoni

IPC: G05B13/04 ,  G05B11/01 ,  H03K3/00

CPC classification number: G06F1/025

Abstract: A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.

Abstract translation: 一种用于产生根据机器的当前状态产生不同信号的信号的状态机。 状态机被配置为根据内部定时器的功能改变状态，并且作为表示状态机外部的事件的信号的函数。

公开(公告)号：US20100164400A1

公开(公告)日：2010-07-01

申请号：US12643883

申请日：2009-12-21

Applicant: Claudio ADRAGNA

Inventor： Claudio ADRAGNA

IPC: H05B41/36

CPC classification number: H02M1/4225 ,  H02M1/44 ,  H02M3/3376 ,  H02M2001/007 ,  H05B33/0815 ,  H05B33/0848 ,  Y02B20/347 ,  Y02B70/126 ,  Y02B70/1433

Abstract: A switching power supply for supplying a load requiring a controlled current includes a PFC pre-regulator for receiving an input voltage and providing an output voltage, and a DC-DC switching converter for receiving at input the voltage output by the pre-regulator and for providing at output a supply voltage of said load. The switching DC-DC converter operates at a fixed and constant operating frequency, is a resonant converter and includes an LLC resonant circuit.

Abstract translation: 用于提供需要受控电流的负载的开关电源包括用于接收输入电压并提供输出电压的PFC预调节器，以及DC-DC开关转换器，用于在输入端接收预调节器输出的电压， 在输出端提供所述负载的电源电压。 开关DC-DC转换器工作在固定和恒定的工作频率，是谐振转换器，并且包括一个LLC谐振电路。

公开(公告)号：US6028468A

公开(公告)日：2000-02-22

申请号：US749414

申请日：1996-11-15

Applicant: Pietro Menniti ,  Aldo Novelli

Inventor： Pietro Menniti ,  Aldo Novelli

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: A level shift circuit for a voltage input signal (S, SN) presenting at least a first and a second high-voltage levels, the circuit comprising two parallel branches, each formed by a current modulator and a signal converter. The current modulators are supplied with two signals in phase opposition to each other, and generate current signals whose value depends on the level of the respective input signal; and the signal converters convert the current signals into ground-related voltage signals. The signal converters together form a single-ended differential circuit, the output of which therefore presents a low-voltage digital signal which can be processed by normal digital circuits and is unaffected by noise or variations in supply voltage.

Abstract translation: 一种用于至少呈现第一和第二高电压电平的电压输入信号（S，SN）的电平移位电路，所述电路包括两个平行分支，每个分支由电流调制器和信号转换器形成。 电流调制器被提供有彼此相位相反的两个信号，并产生其值取决于相应输入信号的电平的电流信号; 并且信号转换器将电流信号转换成与地相关的电压信号。 信号转换器一起形成单端差分电路，其输出因此呈现可由普通数字电路处理的低电压数字信号，并且不受噪声或电源电压变化的影响。

公开(公告)号：US20240212714A1

公开(公告)日：2024-06-27

申请号：US18597484

申请日：2024-03-06

Applicant: STMicroelectronics KK ,  STMicroelectronics S.r. l.

Inventor： Marco Ferrari ,  Davide Betta ,  Diego Tognoli ,  Roberto Trabattoni

IPC: G11B21/08

CPC classification number: G11B21/083

Abstract: In accordance with an embodiment, a hard disk drive includes voice coil motors (VCMs) coupled to respective control units configured to drive retract an operation of the VCMs in the hard disk drive. The retract operation of the VCMs includes a sequence of retract steps. The control units are allotted respective time slots for communication over a communication line with the respective time slots synchronized via the common clock line, and are configured to drive sequences of retract steps of the VCMs in the hard disk drive in a timed relationship.

公开(公告)号：US6075750A

公开(公告)日：2000-06-13

申请号：US186497

申请日：1998-11-04

Applicant: Giovanni Campardo ,  Rino Micheloni ,  Marco Maccarrone ,  Matteo Zammattio

Inventor： Giovanni Campardo ,  Rino Micheloni ,  Marco Maccarrone ,  Matteo Zammattio

IPC: G11C8/18 ,  G11C8/00

CPC classification number: G11C8/18

Abstract: A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.

Abstract translation: 一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。 该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。

公开(公告)号：US20240160593A1

公开(公告)日：2024-05-16

申请号：US18056012

申请日：2022-11-16

Applicant: STMicroelectronics S.r..l.

Inventor： Marco Castellano ,  Francesco Bruni ,  Luca Gandolfi ,  Marco Leo

IPC: G06F13/40

CPC classification number: G06F13/4068 ,  G06F2213/40

Abstract: A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.