公开(公告)号：US20070075739A1

公开(公告)日：2007-04-05

申请号：US11539777

申请日：2006-10-09

申请人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

发明人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US06980029B1

公开(公告)日：2005-12-27

申请号：US10319720

申请日：2002-12-13

申请人： Ashok Vittal ,  Hare K. Verma

发明人： Ashok Vittal ,  Hare K. Verma

IPC分类号： H03K19/177

CPC分类号： H03K19/177

摘要： A programmable logic device has a plurality of levels of programmable logic modules with fixed interconnections. The outputs of a level connect to inputs of the next level of programmable logic modules. The first level is fed from a bank of memory elements and the inputs to this bank of memory elements are derived from the last level. Crossbar switches are optionally inserted between a carefully chosen pairs of levels.

摘要翻译： 可编程逻辑器件具有多个级别的具有固定互连的可编程逻辑模块。 电平的输出连接到下一级可编程逻辑模块的输入。 第一级从存储器元件组馈送，并且存储元件组的输入从最后一级派生。 交叉开关可选地插入精心挑选的水平对之间。

公开(公告)号：US20080082951A1

公开(公告)日：2008-04-03

申请号：US11537744

申请日：2006-10-02

申请人： Bo Hu

发明人： Bo Hu

IPC分类号： G06F17/50 ,  H03K19/00

CPC分类号： G06F17/5054

摘要： A method for clustering logic units in a field programmable integrated chip to generate a set of clusters is disclosed. The clustering step for forming a super cluster comprises a first logic element and a second logic unit a first logic unit and a super cluster, or a first super cluster and a second super cluster. The method includes generating all possible configurations by enumerating all possible two-way relationships combining a driver-and-receiver relationship from a pool of a finite number of dedicated connections. The set of all possible configurations is reduced to a subset of configurations based on one or more multi-dimension criteria. Each dimension in the multi-dimensional criteria is represented by a parameter. The method involves prioritizing a collection of parameters so that a set of selected parameters or a set of selected criteria is used to generate a desirable number of subsets of configurations.

摘要翻译： 公开了一种用于对现场可编程集成芯片中的逻辑单元进行聚类以产生一组簇的方法。 用于形成超级群集的聚类步骤包括第一逻辑单元和第二逻辑单元，第一逻辑单元和超群集，或第一超群和第二超群。 该方法包括通过枚举从有限数量的专用连接的池组合驱动器和接收器关系的所有可能的双向关系来生成所有可能的配置。 所有可能的配置的集合基于一个或多个多维标准被减少到一个配置的子集。 多维标准中的每个维度都由一个参数表示。 该方法涉及对参数集合进行优先级排序，以便使用一组所选择的参数或一组选择的标准来生成期望数量的配置子集。

公开(公告)号：US20070085565A1

公开(公告)日：2007-04-19

申请号：US11539799

申请日：2006-10-09

申请人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

发明人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. It a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US20070085564A1

公开(公告)日：2007-04-19

申请号：US11539757

申请日：2006-10-09

申请人： Hare Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

发明人： Hare Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.

摘要翻译： 公开了一种使用输入逻辑路由单元（ILRC）多路复用器和输出逻辑路由单元（OLRC）多路复用器进行专用逻辑单元之间的本地连接的可编程逻辑结构。 在简单的可编程逻辑结构中，专用逻辑单元（DLC）以包括用于端口A的多个ILRC多路复用器和用于端口B的多个OLRC多路复用器的可编程逻辑结构实现。在多级可编程逻辑结构中，多列专用逻辑 单元被设计成具有彼此相邻的专用本地单元的列，其中每个DLC列用于实现特定的逻辑功能。 在第一实施例中，可以在专用逻辑单元之间进行本地连接。 在L级的第一个DLC中的OLRC在L + 1级的第二个DLC中与ILRC进行本地点对点连接。 在第二实施例中，可以从任何其他专用逻辑单元进行本地连接，无论相对于相对点或多路复用器是水平还是垂直的，以及来自当前逻辑和路由单元（LRC）的任何偏移。 在第三实施例中，可以通过将第一OLRC拼接到第二OLRC（用于连接到ILRC）来实现本地连接，这允许来自其他列或DLC级的线路到达用于快速本地互连的ILRC。

公开(公告)号：US20070080711A1

公开(公告)日：2007-04-12

申请号：US11539809

申请日：2006-10-09

申请人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri ,  Elliott Delaye

发明人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US20070075741A1

公开(公告)日：2007-04-05

申请号：US11539825

申请日：2006-10-09

申请人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

发明人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US20070075740A1

公开(公告)日：2007-04-05

申请号：US11539790

申请日：2006-10-09

申请人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

发明人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an NOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“或非”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US07176717B2

公开(公告)日：2007-02-13

申请号：US11036109

申请日：2005-01-14

申请人： Ravi Sunkavalli ,  Hare K. Verma ,  Chandra Mulpuri ,  Elliott Delaye

发明人： Ravi Sunkavalli ,  Hare K. Verma ,  Chandra Mulpuri ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： A programmable logic structure is disclosed that has a set of dedicated lines which extend internally throughout different dedicated logic cells within a logic and routing block (LRB), extend from a previous logic routing block to the present logic and routing block, or extend from the present logic and routing block to the next logic and routing block. One set of dedicated lines from a first logic and routing block can be stitched to another set of dedicated lines of a second logic and routing block for extending the reach as well as bypassing a logic and routing block, or bypassing a dedicated logic cell in the same logic and routing block. The dedicated lines between logic and routing blocks allow a logic and routing block to receive more inputs from its own switch box or to drive more outputs than provided by the logic and routing block as specified by a given function.

摘要翻译： 公开了一种可编程逻辑结构，其具有一组专用线，其在逻辑和路由块（LRB）内的不同专用逻辑单元内部扩展，从先前的逻辑路由块延伸到当前逻辑和路由块，或者从 将逻辑和路由块提供给下一个逻辑和路由块。 来自第一逻辑和路由块的一组专用线可以被缝合到第二逻辑和路由块的另一组专用线，用于扩展覆盖范围以及绕过逻辑和路由块，或绕过逻辑和路由块中的专用逻辑单元 相同的逻辑和路由块。 逻辑和路由块之间的专用线允许逻辑和路由块从其自己的开关盒接收更多的输入，或者驱动比由给定功能指定的逻辑和路由块提供的更多的输出。

公开(公告)号：US20060186919A1

公开(公告)日：2006-08-24

申请号：US11066336

申请日：2005-02-23

申请人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

发明人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。