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1.发明授权Abstraction level-preserving conversion of flip-flop-inferred hardware description language (HDL) to instantiated HDL 失效触发器推断硬件描述语言（HDL）到实例化HDL的抽象级别保留转换公开(公告)号：US08443314B1
公开(公告)日：2013-05-14
申请号：US13403388
申请日：2012-02-23
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A logic design and synthesis program, method and system provides intelligibility and independence of separate blocks in digital logic designs at the synthesis level. The sequential and combinational logic are separated and the sequential logic is then mapped to flip-flop library components. State-retaining elements, i.e., flip-flops detected in the input hardware description language (HDL) are represented in the sequential logic HDL output. The combinational logic HDL and the sequential logic HDL are connected only by signals, so signals are introduced to represent the flip-flop signals and variables detected in the input HDL. The sequential and combinational logic HDL are then synthesized to produce the design.
摘要翻译： 逻辑设计和合成程序，方法和系统在合成级别提供数字逻辑设计中的单独块的可理解性和独立性。 顺序和组合逻辑被分离，然后将顺序逻辑映射到触发器库组件。 状态保持元件，即在输入硬件描述语言（HDL）中检测到的触发器在顺序逻辑HDL输出中被表示。 组合逻辑HDL和顺序逻辑HDL仅通过信号连接，因此引入信号以表示在输入HDL中检测的触发器信号和变量。 然后合成顺序和组合逻辑HDL以产生设计。
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2.发明授权公开(公告)号：US08140313B2
公开(公告)日：2012-03-20
申请号：US12022309
申请日：2008-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F9/4484
摘要： A method, system and computer program product for modeling variables in subprograms of a HDL program. A subprogram is provided with an initial value of a variable of an element being modeled and the subprogram is stored in memory of a data processing system. In response to a subprogram call, a copy of the stored subprogram is provided to the requesting HDL program. During execution, the initial value of the variable in the provided copy of the subprogram may be modified by the HDL program, but the value retains unchanged in the stored subprogram.
摘要翻译： 一种用于对HDL程序子程序中的变量进行建模的方法，系统和计算机程序产品。 子程序被提供有被建模的元件的变量的初始值，并且子程序被存储在数据处理系统的存储器中。 响应于子程序调用，将所存储的子程序的副本提供给请求的HDL程序。 在执行期间，子程序提供的副本中的变量的初始值可以由HDL程序修改，但是该值在存储的子程序中保持不变。
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3.发明申请Method, System and Program Product Supporting Sequential Encoding for Relational Analysis (SERA) of a Software Model 有权方法，系统和程序产品支持软件模型的关系分析（SERA）的顺序编码公开(公告)号：US20080209389A1
公开(公告)日：2008-08-28
申请号：US11677652
申请日：2007-02-22
IPC分类号： G06F9/44
CPC分类号： G06F8/43
摘要： A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system, and following the transforming, the software system is verified based upon the sequential logic representation. Following verification, results of verification of the software system are output.
摘要翻译： 验证软件系统的方法包括接收使用高级建模语言描述的软件系统的描述，并且响应于此，解析描述并构造抽象语法图。 抽象语法图被转换为软件系统的顺序逻辑表示，并且在变换之后，基于顺序逻辑表示验证软件系统。 验证后，输出软件系统的验证结果。
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公开(公告)号：US08234604B2
公开(公告)日：2012-07-31
申请号：US12202500
申请日：2008-09-02
申请人： Ali S El-Zein , Fadi A Zaraket
发明人： Ali S El-Zein , Fadi A Zaraket
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/86 , Y02T10/82
摘要： Co-Optimization utilizing Symbolic Execution (COSE) works across components of an embedded design to optimize structures therein. COSE utilizes symbolic execution (SE) to analyze software components and defines a limited set of values that software feeds hardware as constraints. SE explores substantially all possible paths of execution of the code specifying a component. It accomplishes this by accumulating path conditions (PCs) and annotating them to the corresponding segments of the component. A PC is associated with a branch of code and consists of the conjunction of conditions over input and state variables necessary and sufficient for the branch to execute. These PCs define constraints that limit the set of values that software feeds hardware. These constraints are then propagated across the networks of the design and employ static analysis techniques such as constant propagation, redundancy removal, and don't care optimizations to reduce the hardware components.
摘要翻译： 利用符号执行（COSE）的协同优化在嵌入式设计的组件中工作，以优化其中的结构。 COSE利用符号执行（SE）来分析软件组件，并定义一组有限的值，软件将硬件提供给约束。 SE基本上探索了指定组件的代码的所有可能的执行路径。 它通过累积路径条件（PC）并将其注释到组件的相应段来实现。 PC与代码分支相关联，并且由对分支执行所必需的足够的输入和状态变量的条件的结合组成。 这些PC定义了限制软件提供硬件的值集合的约束。 然后，这些约束在设计网络中传播，并采用静态分析技术，例如恒定传播，冗余删除，并且不关心优化以减少硬件组件。
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公开(公告)号：US20100058256A1
公开(公告)日：2010-03-04
申请号：US12202500
申请日：2008-09-02
申请人： ALI S. EL-ZEIN , Fadi A. Zaraket
发明人： ALI S. EL-ZEIN , Fadi A. Zaraket
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/86 , Y02T10/82
摘要： Co-Optimization utilizing Symbolic Execution (COSE) works across components of an embedded design to optimize structures therein. COSE utilizes symbolic execution (SE) to analyze software components and defines a limited set of values that software feeds hardware as constraints. SE explores substantially all possible paths of execution of the code specifying a component. It accomplishes this by accumulating path conditions (PCs) and annotating them to the corresponding segments of the component. A PC is associated with a branch of code and consists of the conjunction of conditions over input and state variables necessary and sufficient for the branch to execute. These PCs define constraints that limit the set of values that software feeds hardware. These constraints are then propagated across the networks of the design and employ static analysis techniques such as constant propagation, redundancy removal, and don't care optimizations to reduce the hardware components.
摘要翻译： 利用符号执行（COSE）的协同优化在嵌入式设计的组件中工作，以优化其中的结构。 COSE利用符号执行（SE）来分析软件组件，并定义一组有限的值，软件将硬件提供给约束。 SE基本上探索了指定组件的代码的所有可能的执行路径。 它通过累积路径条件（PC）并将其注释到组件的相应段来实现。 PC与代码分支相关联，并且由对分支执行所必需的足够的输入和状态变量的条件的结合组成。 这些PC定义了限制软件提供硬件的值集合的约束。 然后，这些约束在设计网络中传播，并采用静态分析技术，例如恒定传播，冗余删除，并且不关心优化以减少硬件组件。
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6.发明授权公开(公告)号：US08141048B2
公开(公告)日：2012-03-20
申请号：US11677652
申请日：2007-02-22
CPC分类号： G06F8/43
摘要： A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system. The sequential logic representation is formed by reference to a Hardware Description Language (HDL) library. Then, the sequential logic representation is transformed into a gate-level sequential logic representation. Following the transforming, the software system is verified based upon the gate-level sequential logic representation. Following verification, results of verification of the software system are output.
摘要翻译： 验证软件系统的方法包括接收使用高级建模语言描述的软件系统的描述，并且响应于此，解析描述并构造抽象语法图。 抽象语法图被转换成软件系统的顺序逻辑表示。 通过参考硬件描述语言（HDL）库形成顺序逻辑表示。 然后，顺序逻辑表示被转换成门级顺序逻辑表示。 在变换之后，基于门级顺序逻辑表示验证软件系统。 验证后，输出软件系统的验证结果。
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7.发明授权Method for reconfiguration of random biases in a synthesized design without recompilation 有权在没有重新编译的情况下，在合成设计中重新配置随机偏差的方法公开(公告)号：US07284210B2
公开(公告)日：2007-10-16
申请号：US11050232
申请日：2005-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method, system and computer program product for performing testing and verification is disclosed. The method includes converting a bias data specification to a driver specification. The driver specification is then parsed into a base constraint and bias file, wherein the base constraint and bias file is suitable for conversion into one of a set comprising a netlist representation and a random simulation representation. A verification framework is selected from among a set comprising a random verification framework using the random simulation representation and a synthesized verification framework using the netlist representation. In response to selecting the random verification framework using the random simulation representation, the random simulation representation is compiled into a parameter database. In response to selecting the synthesized verification framework using the netlist representation, the netlist representation is compiled into a synthesized model. A property of at least one of a set of the synthesized model and the parameter database is tested and verified.
摘要翻译： 公开了一种用于执行测试和验证的方法，系统和计算机程序产品。 该方法包括将偏置数据规范转换为驱动器规范。 然后将驱动器规范解析为基本约束和偏置文件，其中基本约束和偏置文件适于转换成包括网表表示和随机模拟表示的集合之一。 从包括使用随机模拟表示的随机验证框架的集合和使用网表表示的合成验证框架中选择验证框架。 响应于使用随机模拟表示法选择随机验证框架，随机模拟表示被编译成参数数据库。 响应于使用网表表示来选择合成的验证框架，网表表示被编译成合成模型。 测试和验证合成模型和参数数据库中的至少一个的属性。
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