公开(公告)号：US06563375B1

公开(公告)日：2003-05-13

申请号：US09688778

申请日：2000-10-16

申请人： Abolfazl Khosrowbeygi ,  Sudhir Aggarwal

发明人： Abolfazl Khosrowbeygi ,  Sudhir Aggarwal

IPC分类号： H03B100

CPC分类号： H03G1/0023

摘要： According to a particular example application, the present invention is embodied in the form of first and second current-steering sections arranged to steer a differential current input signal. Each of the first and second current-steering sections is current driven via differential current paths. The first current-steering section configured and arranged to source current and thereby drive the second current-steering section. Another aspect of the invention employs stacked Gilbert cells, as described above, to form a variable gain amplifier (“VGA”) circuit that achieves a large dynamic range, a wide frequency response and improved linearity, while consuming relatively low amounts of power.

摘要翻译： 根据具体示例应用，本发明以布置成转向差动电流输入信号的第一和第二电流转向部分的形式实现。 第一和第二电流转向部分中的每一个电流通过差动电流路径驱动。 第一电流导向部构造和布置成源电流，从而驱动第二电流转向部。 如上所述，本发明的另一方面采用堆叠的吉尔伯特单元，以形成可变增益放大器（“VGA”）电路，其在消耗相对低的功率的同时实现大的动态范围，宽的频率响应和改善的线性度。

公开(公告)号：US06804499B2

公开(公告)日：2004-10-12

申请号：US09829105

申请日：2001-04-09

申请人： Abolfazl Khosrowbeygi ,  Petrus M. Stroet

发明人： Abolfazl Khosrowbeygi ,  Petrus M. Stroet

IPC分类号： H01Q1112

CPC分类号： H03D7/1425 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0023 ,  H03D2200/0033 ,  H03D2200/0043

摘要： A power mixer architecture for a transmitter chip is disclosed. The power mixer architecture is a mixing stage including one or more upper trees, and one or more lower trees. Each lower tree is selectively activated to receive current biasing signals, and current intermediate frequency signals. Upon receipt, the activated lower tree activates a corresponding upper tree to receive one or more amplified current intermediate frequency signals from the lower tree. In conjunction with a reception of voltage local oscillating signals, the upper tree provides voltage radio frequency signals. The gain of the lower tree is designed to be constant over any variance in a temperature, supply voltage or processing performance of the transmitter chip.

摘要翻译： 公开了用于发射机芯片的功率混频器架构。 动力混合器结构是混合阶段，包括一个或多个上部树木，以及一个或多个较低的树木。 选择性地激活每个下层树以接收电流偏置信号和当前的中频信号。 在接收到时，激活的下层树启动相应的上层树，以从下层树接收一个或多个放大的当前中频信号。 结合接收电压本地振荡信号，上层树提供电压射频信号。 下层树的增益被设计为在发射器芯片的温度，电源电压或处理性能的任何变化上都是恒定的。

公开(公告)号：US06889038B2

公开(公告)日：2005-05-03

申请号：US09827625

申请日：2001-04-06

申请人： Abolfazl Khosrowbeygi

发明人： Abolfazl Khosrowbeygi

IPC分类号： H03F3/45 ,  H03G3/30 ,  H04B1/04 ,  H04B1/28

CPC分类号： H04B1/04 ,  H03F1/02 ,  H03F3/24 ,  H03F3/45089 ,  H04B2001/045

摘要： A dynamic biasing of a transmitter chip is disclosed. The transmitter chip comprises a variable gain amplifying stage, a biasing stage, a phase shifting stage, and a mixing stage. In response to a voltage control signal and a voltage intermediate frequency signal, the variable gain amplifying stage provides a current drive signal and a DC current control signal. While an ampere level of the DC component of the current drive signal and an ampere level of the DC current control signal vary as a function of any variations in the voltage control signal as well as any variation in the temperature, process performance, and supply power of the transmitter chip, a ratio of the ampere level of a DC component of the current drive signal to the ampere level of the DC current control signal is constant. The current drive signal and the DC current control signal establish the dynamic biasing block in a current mode of operation that maintains a constant gain of the mixing stage.

摘要翻译： 公开了一种发射机芯片的动态偏置。 发射机芯片包括可变增益放大级，偏置级，相移级和混频级。 响应于电压控制信号和电压中频信号，可变增益放大级提供电流驱动信号和直流电流控制信号。 当电流驱动信号的DC分量的安培电平和DC电流控制信号的安培电平作为电压控制信号的任何变化以及温度，过程性能和电源的任何变化的函数而变化时 发射机芯片的电流驱动信号的直流分量的安培电平与直流电流控制信号的安培电平的比率是恒定的。 当前驱动信号和直流电流控制信号在当前的操作模式下建立动态偏置块，其保持混合级的恒定增益。

公开(公告)号：US06531922B1

公开(公告)日：2003-03-11

申请号：US09688773

申请日：2000-10-16

申请人： Abolfazl Khosrowbeygi ,  Hongyu Li

发明人： Abolfazl Khosrowbeygi ,  Hongyu Li

IPC分类号： H03F304

CPC分类号： H02M3/00 ,  H02M2001/007

摘要： The present invention is directed to advantages discovered in connection with controlling DC current passing between and adversely affecting cascaded current-mode blocks. According to a particular example application, the present invention includes first and second cascaded current-mode circuit blocks, and a circuit-replication and comparison block adapted to replicate the operation and output impedance of the first current-mode circuit block and to replicate the operation and input impedance of the second current-mode circuit block. This replication-comparison block includes a differential comparator adapted to detect and correct for a voltage differential corresponding to current passing from the first current-mode circuit block and the second current-mode circuit block. This approach can result in a number advantages relating to improvements in terms of various operational aspects including, for example, reductions in power consumption.

摘要翻译： 本发明涉及在控制直流电流之间发现的优点，并且不利地影响级联电流模式块。 根据具体示例应用，本发明包括第一和第二级联电流模式电路块，以及电路复制和比较块，其适于复制第一电流模式电路块的操作和输出阻抗并复制操作 和第二电流模式电路块的输入阻抗。 该复制比较块包括差分比较器，其适于检测和校正与从第一电流模式电路块和第二电流模式电路块通过的电流相对应的电压差。 这种方法可以产生与各种操作方面的改进有关的许多优点，包括例如功率消耗的降低。