公开(公告)号：US20040210794A1

公开(公告)日：2004-10-21

申请号：US10825717

申请日：2004-04-16

申请人： Adaptec, Inc.

发明人： Alexander H. Frey ,  Keith E. Conner

IPC分类号： G06F012/16

CPC分类号： G06F11/1076 ,  G06F11/20 ,  G06F2211/1028

摘要： Efficient buffer cache utilization frees a data buffer as soon as data buffer processing is completed, and without losing association of the freed data buffer and a descriptor buffer. Separate free buffer link lists identify the freed data buffer and any freed descriptor buffer. The data buffer is rapidly processed then freed generally before completion of processing of the descriptor buffer, freeing the processed associated data buffer before the associated descriptor buffer is freed. The association of the processed free data buffer and the descriptor buffer may be ended to enable the more frequent use of the large capacity data buffer for other update requests.

摘要翻译： 一旦数据缓冲区处理完成，高效缓冲区高速缓存利用就释放数据缓冲区，并且不会丢失释放的数据缓冲区和描述符缓冲区的关联。 单独的空闲缓冲区链接列表标识释放的数据缓冲区和任何释放的描述符缓冲区。 数据缓冲区被快速处理，然后在完成描述符缓冲器的处理之前被释放，在关联的描述符缓冲器被释放之前释放处理后的关联数据缓冲器。 可以结束处理的空闲数据缓冲器和描述符缓冲器的关联，以便更频繁地使用大容量数据缓冲器用于其他更新请求。

公开(公告)号：US20040210610A1

公开(公告)日：2004-10-21

申请号：US10726427

申请日：2003-12-02

申请人： ADAPTEC, INC.

发明人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

IPC分类号： G06F007/00

CPC分类号： G06F5/01 ,  G06F7/49994

摘要： A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second operand has a greater bit width than the first operand. Next, the first operand is transformed by aligning a least significant bit of the first operand to a lowest bit position of a transformed operand having a bit size equal to the second operand. Then, the bits of the transformed operand are sign extended and padded in a manner to allow carry propagation. Next, the transformed operand is transmitted to the processor. A method for shifting operands and a processor are also provided.

摘要翻译： 提供了一种透明地呈现不同大小的待处理操作数的方法。 该方法通过提供具有第一位宽的第一操作数来启动。 然后，确定与处理器相关联的第二操作数的位宽度。 第二个操作数的位宽比第一个操作数大。 接下来，通过将第一操作数的最低有效位与具有等于第二操作数的位大小的变换操作数的最低位位置对齐来变换第一操作数。 然后，变换的操作数的位被符号扩展并以允许进位传播的方式填充。 接下来，将变换的操作数传送到处理器。 还提供了用于移位操作数和处理器的方法。

公开(公告)号：US20040153494A1

公开(公告)日：2004-08-05

申请号：US10718270

申请日：2003-11-19

申请人： ADAPTEC, INC.

发明人： Shridhar Mukund ,  Anjan Mitra ,  Mahesh Gopalan

IPC分类号： G06F015/16

CPC分类号： H04L49/3063 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161

摘要： A method for efficiently processing layers of a data packet is provided. The method initiates with defining a pipeline of processors communicating with a distributed network and CPU of a host system. Then, a data packet from the distributed network is received into a first stage of the pipeline. Next, the data packet is processed to remove a header associated with the first stage. Then, the processed data packet is transmitted to a second stage. The operations of processing and transmitting the processed data packet are repeated for successive stages until a header associated with a final stage has been removed. Then, the data packet is transmitted to the CPU of the host system. It should be appreciated that the header is not necessarily transformed at each stage. For example, suitable processing that does not strip the header may be applied at each stage.

摘要翻译： 提供了一种用于有效处理数据分组的层的方法。 该方法通过定义与主机系统的分布式网络和CPU通信的处理器流水线来启动。 然后，来自分布式网络的数据分组被接收到流水线的第一级。 接下来，处理数据分组以移除与第一阶段相关联的报头。 然后，处理的数据分组被发送到第二阶段。 处理和发送处理的数据分组的操作重复连续阶段，直到与最后一级相关联的报头已经被去除。 然后，将数据包发送到主机系统的CPU。 应当理解，头部不一定在每个阶段变换。 例如，可以在每个阶段应用不剥离报头的适当处理。

公开(公告)号：US20040153302A1

公开(公告)日：2004-08-05

申请号：US10712711

申请日：2003-11-12

申请人： ADAPTEC, INC.

发明人： Shridhar Mukund ,  Jinesh Parikh

IPC分类号： G06F017/50

CPC分类号： G06F17/5022

摘要： A method for simulating a chip is provided. The method initiates with defining a library of components for a processor. Then, the interconnections for a set of pipelined processors including the processor are defined. Next, a processor circuit is generated by combining the library of components and the interconnections for the set of pipelined processors. Then, a code representation of a model of the set of pipelined processors is generated. Next, the signals generated by the code representation are compared to the signals generated by the processor circuit. If the comparison of the signals is unacceptable, then the method includes identifying a cause of the unacceptable comparison of the signals at a block level of the processor circuit. A method for generating a netlist for a pipeline of processors, a method for debugging the processor circuit and computer code for simulating a chip circuit are also provided.

摘要翻译： 提供了一种用于模拟芯片的方法。 该方法通过定义处理器的组件库来启动。 然后，定义一组包括处理器的流水线处理器的互连。 接下来，通过组合用于一组流水线处理器的组件库和互连来生成处理器电路。 然后，生成流水线处理器集合的模型的代码表示。 接下来，将由码表示产生的信号与由处理器电路产生的信号进行比较。 如果信号的比较是不可接受的，则该方法包括识别在处理器电路的块级别处的信号的不可接受的比较的原因。 还提供了一种用于生成处理器流水线的网表的方法，用于调试处理器电路的方法和用于模拟芯片电路的计算机代码。

公开(公告)号：US20020017920A1

公开(公告)日：2002-02-14

申请号：US09965210

申请日：2001-09-26

申请人： Adaptec, Inc.

发明人： Walter Francis Bridgewater JR.

IPC分类号： H03K019/0175

CPC分类号： H04L25/0292 ,  G06F13/4072 ,  H03K19/018514 ,  H04L25/026 ,  H04L25/0272 ,  H04L25/0276 ,  Y02D10/14 ,  Y02D10/151

摘要： A low-voltage differential dual receiver for a SCSI bus uses a symmetrical driver by doing without a termination bias voltage. The data phase and protocol phase of SCSI communication are separated by using two receivers and optimizing each receiver for its particular function. A high-speed receiver is used when transmitting data at high-speeds, and a lower performance, low-speed receiver is used for other SCSI phases. A built-in offset allows the low-speed receiver to operate correctly during bus arbitration. The built-in offset in the low-speed receiver takes the place of the termination bias voltage in a traditional SCSI bus and is implemented in a variety of ways. In a first embodiment, an N-well generation circuit produces a bulk voltage for one transistor of the differential transistor pair that is different than a supply voltage supplied to the bulk of the other transistor. In a second embodiment, each of the transistors of the pair is implanted with a different dosage to change the threshold voltage for each. In a third embodiment, resistors of different sizes are attached to the source of each transistor in the pair in order to produce a different voltage at each source. In a fourth embodiment, two replica comparators are used to monitor an offset voltage of the differential receiver and to send control signals to an adjustable current source. The current source is adjusted by having an up-down counter switch on and off various legs of the current source.

摘要翻译： 用于SCSI总线的低压差分双接收器通过在没有端接偏置电压的情况下使用对称驱动器。 通过使用两个接收器分离SCSI通信的数据阶段和协议阶段，并针对其特定功能优化每个接收机。 在高速传输数据时使用高速接收机，其他SCSI阶段使用较低性能的低速接收机。 内置偏移允许低速接收机在总线仲裁期间正确运行。 低速接收机中的内置偏移量代替了传统SCSI总线中的端接偏置电压，并以各种方式实现。 在第一实施例中，N阱产生电路为差分晶体管对的一个晶体管产生不同于提供给另一晶体管本体的电源电压的体电压。 在第二实施例中，该对中的每个晶体管被注入不同的剂量以改变每个的阈值电压。 在第三实施例中，不同尺寸的电阻器被连接到该对中的每个晶体管的源极，以便在每个源处产生不同的电压。 在第四实施例中，使用两个复制比较器来监视差分接收器的偏移电压并将控制信号发送到可调电流源。 通过使电流源的各个支路有一个上下计数器开关来调节电流源。

公开(公告)号：US20040073724A1

公开(公告)日：2004-04-15

申请号：US10682164

申请日：2003-10-08

申请人： Adaptec, Inc.

发明人： Andrew W. Wilson ,  Paul J. von Stamwitz ,  John Carrier ,  Renato Maranon ,  John Tai

IPC分类号： G06F003/00

CPC分类号： H04L49/9094 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9063 ,  H04L69/16 ,  H04L69/22 ,  H04L69/32

摘要： A network stack layer interface is provided for efficient communication between network stack layers. The network stack layer interface includes a header portion that defines various characteristics of the network stack layer interface. In addition, a buffer descriptor is included that defines data that was, or will be, transmitted over the computer network. The buffer descriptor includes a memory address pointer to the data. In this manner, information is passed between network stack layers via the network stack interface, resulting in fast network data transfer with reduced data copying.

摘要翻译： 提供网络堆叠层接口用于网络堆叠层之间的有效通信。 网络堆栈层接口包括一个头部部分，它定义了网络堆叠层接口的各种特性。 另外还包括定义已经或将要通过计算机网络传输的数据的缓冲区描述符。 缓冲描述符包括一个指向数据的存储器地址指针。 以这种方式，信息通过网络堆栈接口在网络堆叠层之间传递，导致快速的网络数据传输，减少数据复制。

公开(公告)号：US20020059372A1

公开(公告)日：2002-05-16

申请号：US09993447

申请日：2001-11-13

申请人： Adaptec, Inc.

发明人： Michael Goshev ,  Maureen McMahon

IPC分类号： G06F015/16

CPC分类号： H04L29/08846 ,  G06F3/1222 ,  G06F3/1239 ,  G06F3/1288 ,  G06F9/468 ,  G06F21/82 ,  H04L67/12 ,  H04L69/329 ,  Y10S707/99938 ,  Y10S707/99939

摘要： Disclosed is a system for transparently sharing peripheral devices over a network. The system includes a first computer having at least one peripheral device, and a second computer that is networked to the first computer. The second computer is configured to send a request to use the at least one peripheral device over the network, and the request is processed to determine whether the second computer has sharing privileges to use the at least one peripheral device. Furthermore, the first computer is configured to grant access to the request of the second computer if the second computer has the sharing privileges that enable access to the at least one peripheral device. In this embodiment, the first computer acts as a Server that can share its peripheral devices, and the second computer acts as a Client that access the Server's peripheral devices.