-
1.发明申请HYBRID BUILT-IN SELF TEST (BIST) ARCHITECTURE FOR EMBEDDED MEMORY ARRAYS AND AN ASSOCIATED METHOD 有权用于嵌入式存储器阵列和相关方法的混合内置自检（BIST）架构公开(公告)号：US20080178053A1
公开(公告)日：2008-07-24
申请号：US12057405
申请日：2008-03-28
CPC分类号： G01R31/31724 , G11C29/14 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.
摘要翻译： 公开了内置自检（BIST）架构的实施例，其包括以较低频率操作以远程执行多个嵌入式存储器阵列共同的测试功能的独立控制器。 该架构还包含与嵌入式存储器阵列相关联的命令乘法器，并且选择性地以两种不同模式之一操作：正常模式或旁路模式。 在正常模式下，来自控制器的指令相乘，使得存储器阵列特定的测试功能可以在每个特定存储器阵列的较高工作频率下本地执行。 而在旁路模式中，指令的乘法被暂停，使得可以在控制器的较低工作频率下本地执行存储器阵列特定的测试功能。 在本地执行测试功能的频率变化的能力允许更多的测试模式灵活性。
-
2.发明授权Hybrid built-in self test (BIST) architecture for embedded memory arrays and an associated method 有权嵌入式内存阵列的混合内置自检（BIST）架构及相关方法公开(公告)号：US07631236B2
公开(公告)日：2009-12-08
申请号：US12057405
申请日：2008-03-28
CPC分类号： G01R31/31724 , G11C29/14 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.
摘要翻译： 公开了内置自检（BIST）架构的实施例，其包括以较低频率操作以远程执行多个嵌入式存储器阵列共同的测试功能的独立控制器。 该架构还包含与嵌入式存储器阵列相关联的命令乘法器，并且选择性地以两种不同模式之一操作：正常模式或旁路模式。 在正常模式下，来自控制器的指令相乘，使得存储器阵列特定的测试功能可以在每个特定存储器阵列的较高工作频率下本地执行。 而在旁路模式中，指令的乘法被暂停，使得可以在控制器的较低工作频率下本地执行存储器阵列特定的测试功能。 在本地执行测试功能的频率变化的能力允许更多的测试模式灵活性。
-
搜索结果
2 条记录 (耗时 0.01 秒)
