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1.发明授权Hybrid built-in self test (BIST) architecture for embedded memory arrays and an associated method 有权嵌入式内存阵列的混合内置自检（BIST）架构及相关方法公开(公告)号：US07631236B2
公开(公告)日：2009-12-08
申请号：US12057405
申请日：2008-03-28
CPC分类号： G01R31/31724 , G11C29/14 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.
摘要翻译： 公开了内置自检（BIST）架构的实施例，其包括以较低频率操作以远程执行多个嵌入式存储器阵列共同的测试功能的独立控制器。 该架构还包含与嵌入式存储器阵列相关联的命令乘法器，并且选择性地以两种不同模式之一操作：正常模式或旁路模式。 在正常模式下，来自控制器的指令相乘，使得存储器阵列特定的测试功能可以在每个特定存储器阵列的较高工作频率下本地执行。 而在旁路模式中，指令的乘法被暂停，使得可以在控制器的较低工作频率下本地执行存储器阵列特定的测试功能。 在本地执行测试功能的频率变化的能力允许更多的测试模式灵活性。
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2.发明申请HYBRID BUILT-IN SELF TEST (BIST) ARCHITECTURE FOR EMBEDDED MEMORY ARRAYS AND AN ASSOCIATED METHOD 有权用于嵌入式存储器阵列和相关方法的混合内置自检（BIST）架构公开(公告)号：US20080178053A1
公开(公告)日：2008-07-24
申请号：US12057405
申请日：2008-03-28
CPC分类号： G01R31/31724 , G11C29/14 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.
摘要翻译： 公开了内置自检（BIST）架构的实施例，其包括以较低频率操作以远程执行多个嵌入式存储器阵列共同的测试功能的独立控制器。 该架构还包含与嵌入式存储器阵列相关联的命令乘法器，并且选择性地以两种不同模式之一操作：正常模式或旁路模式。 在正常模式下，来自控制器的指令相乘，使得存储器阵列特定的测试功能可以在每个特定存储器阵列的较高工作频率下本地执行。 而在旁路模式中，指令的乘法被暂停，使得可以在控制器的较低工作频率下本地执行存储器阵列特定的测试功能。 在本地执行测试功能的频率变化的能力允许更多的测试模式灵活性。
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公开(公告)号：US5878094A
公开(公告)日：1999-03-02
申请号：US879486
申请日：1997-06-10
IPC分类号： H03K5/1252 , H03K17/16 , H04B1/10
CPC分类号： H03K17/162 , H03K5/1252
摘要： A noise detection and delay receiver circuit includes a circuit input and output and a plurality of individual receiver circuits connected to the input having trip points which range from a low trip point to a high trip point. Edge detect circuitry and delay circuitry are used to prevent the output from changing back to the previous state for a period of time immediately after it has just changed state. Multiple transitions of the input voltage across the trip points of the individual receivers are used to delay the response until noise has settled out of the input signal.
摘要翻译： 噪声检测和延迟接收器电路包括电路输入和输出以及连接到具有从低跳变点到高跳变点的跳变点的输入的多个单独的接收器电路。 边缘检测电路和延迟电路用于防止输出在其刚刚改变状态之后立即改变到之前的状态一段时间。 使用各个接收器的跳变点之间的输入电压的多次转换来延迟响应，直到噪声已经从输入信号稳定出来。
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4.发明授权Integrated circuit module having reduced impedance and method of providing the same 失效具有减小阻抗的集成电路模块及其提供方法公开(公告)号：US06177833B1
公开(公告)日：2001-01-23
申请号：US09303293
申请日：1999-04-30
IPC分类号： H01L2500
CPC分类号： H01L23/66 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated semiconductor module of reduced impedance and method utilizing a given chip architecture of the type having a memory circuit and a plurality of off-chip drivers and their I/O pads, the module being constructed in a configuration for operation of said memory circuit with less than the number of available drivers such that there are a number of excess drivers and output pads not used for driver operations, and one or more of these excess drivers and their pads are connected to the power terminals of the chip to provide one or more power paths through these drivers and their associated pads in parallel with the power paths of the operational drivers, and the method includes connecting the excess drivers and their output pads to the power terminals of the chip during its fabrication in a manner to provide additional power paths.
摘要翻译： 一种具有减小阻抗的集成半导体模块和利用具有存储器电路和多个片外驱动器及其I / O焊盘的类型的给定芯片架构的模块，该模块被构造成用于操作所述存储器电路的配置， 小于可用驱动器的数量，使得存在多个驱动器和输出焊盘不用于驱动器操作的数量，并且这些过量驱动器及其焊盘中的一个或多个连接到芯片的电源端子以提供一个或多个 通过这些驱动器的电源路径及其相关联的焊盘与操作驱动器的电源路径并联，并且该方法包括在其制造过程中将多余的驱动器及其输出焊盘连接到芯片的电源端子，以提供额外的电源路径 。
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公开(公告)号：US6088206A
公开(公告)日：2000-07-11
申请号：US60837
申请日：1998-04-15
CPC分类号： H03K17/166
摘要： An off-chip driver (OCD) circuit including a clamp circuit to limit overdrive is provided. The circuit comprises an input signal which is inverted to provide an output signal. The driver circuit is comprised of a source-follower transistor to pull-down the output signal. The clamp circuit actively feeds back the source-follower potential to slow down the OCD and minimize ground bounce and noise that causes circuits to fail and signal integrity to be corrupted. The simple drive and clamp circuit is comprised of three transistors, one resistor, and one capacitor. The OCD slew rate is controlled by a current source and provides an output that changes between a positive voltage and ground. The circuit limits dv/dt without using a large resistor as a source follower, hence minimizing the adverse effect on performance.
摘要翻译： 提供了包括限制过驱动的钳位电路的片外驱动器（OCD）电路。 电路包括一个反相输入信号以提供输出信号。 驱动器电路由源极跟随器晶体管组成，用于下拉输出信号。 钳位电路主动反馈源跟随器电位以减慢OCD并最小化导致电路故障并且信号完整性损坏的接地反弹和噪声。 简单的驱动和钳位电路由三个晶体管，一个电阻器和一个电容器组成。 OCD压摆率由电流源控制，并提供在正电压和地之间变化的输出。 电路限制dv / dt，而不使用大电阻作为源极跟随器，从而最小化对性能的不利影响。
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