公开(公告)号：US09665677B2

公开(公告)日：2017-05-30

申请号：US14729829

申请日：2015-06-03

申请人： Agate Logic Inc.

发明人： Suresh Subramanian ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Jason Golbus ,  Dana L. How

IPC分类号： G11C7/00 ,  G06F17/50 ,  G06F13/16 ,  H03K19/177

CPC分类号： G06F17/5054 ,  G06F13/1668 ,  G06F17/505 ,  G06F17/5077 ,  G11C7/00 ,  H03K19/177 ,  Y02D10/14

摘要： A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

公开(公告)号：US08981813B2

公开(公告)日：2015-03-17

申请号：US13689719

申请日：2012-11-29

申请人： Agate Logic Inc.

发明人： Kai Keung Chan ,  David Tsang ,  Shian-Jiun Fu ,  Chao-Chiang Chen

IPC分类号： G06F7/38 ,  H03K19/177 ,  H03K19/0175 ,  H03K3/02

CPC分类号： H03K19/017581 ,  H03K3/02 ,  H03K19/17736

摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

摘要翻译： 公开了一种包含专用集成电路（“ASIC”）和现场可编程门阵列（“FPGA”）的逻辑处理装置，能够自动连接ASIC和FPGA。 逻辑处理装置在一个方面包括相位调整电路，ASIC和可配置逻辑电路（“CLC”），其中CLC可以是FPGA。 虽然ASIC能够根据ASIC时钟域执行特定功能，但是CLC能够根据FPGA时钟域执行可编程逻辑功能。 相位调整电路用于根据ASIC时钟域和FPGA时钟域来自动促进ASIC和CLC之间的通信。

公开(公告)号：US20130154686A1

公开(公告)日：2013-06-20

申请号：US13689719

申请日：2012-11-29

申请人： Agate Logic Inc.

发明人： Kai Keung Chan ,  David Tsang ,  Shian-Jiun Fu ,  Chao-Chiang Chen

IPC分类号： H03K19/0175 ,  H03K3/02

CPC分类号： H03K19/017581 ,  H03K3/02 ,  H03K19/17736

摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

摘要翻译： 公开了一种包含专用集成电路（“ASIC”）和现场可编程门阵列（“FPGA”）的逻辑处理装置，能够自动连接ASIC和FPGA。 逻辑处理装置在一个方面包括相位调整电路，ASIC和可配置逻辑电路（“CLC”），其中CLC可以是FPGA。 虽然ASIC能够根据ASIC时钟域执行特定功能，但是CLC能够根据FPGA时钟域执行可编程逻辑功能。 相位调整电路用于根据ASIC时钟域和FPGA时钟域来自动促进ASIC和CLC之间的通信。