公开(公告)号：US09665677B2

公开(公告)日：2017-05-30

申请号：US14729829

申请日：2015-06-03

申请人： Agate Logic Inc.

发明人： Suresh Subramanian ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Jason Golbus ,  Dana L. How

IPC分类号： G11C7/00 ,  G06F17/50 ,  G06F13/16 ,  H03K19/177

CPC分类号： G06F17/5054 ,  G06F13/1668 ,  G06F17/505 ,  G06F17/5077 ,  G11C7/00 ,  H03K19/177 ,  Y02D10/14

摘要： A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.