利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.01 秒)

    Integrated circuit modeling, design, and fabrication based on degradation mechanisms
    2.
    发明授权
    Integrated circuit modeling, design, and fabrication based on degradation mechanisms 有权
    基于降解机制的集成电路建模，设计和制造

    公开(公告)号：US07750400B2

    公开(公告)日：2010-07-06

    申请号：US12192850

    申请日：2008-08-15

    申请人： Ajit Shanware ,  Srikanth Krishnan

    发明人： Ajit Shanware ,  Srikanth Krishnan

    IPC分类号： H01L21/00

    CPC分类号： H01L27/092 ,  H01L27/0207

    摘要： An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

    摘要翻译： 集成电路（IC）至少包括第一互补MOS（CMOS）电路，第一CMOS电路包括一个或多个第一n沟道MOS（NMOS）晶体管和一个或多个第一p沟道MOS（PMOS）晶体管，其中 第一NMOS晶体管和第一PMOS晶体管布置在第一CMOS电路中以驱动第一CMOS电路的至少第一公共节点。 第一NMOS晶体管的有效栅极沟道长度的平均值（第一NMOS平均长度）比第一PMOS晶体管的有效栅极沟道长度的平均值（第一PMOS平均长度）至少大2％。

    INTEGRATED CIRCUIT MODELING, DESIGN, AND FABRICATION BASED ON DEGRADATION MECHANISMS
    4.
    发明申请
    INTEGRATED CIRCUIT MODELING, DESIGN, AND FABRICATION BASED ON DEGRADATION MECHANISMS 有权
    基于降解机制的集成电路建模，设计和制造

    公开(公告)号：US20100038683A1

    公开(公告)日：2010-02-18

    申请号：US12192850

    申请日：2008-08-15

    申请人： Ajit Shanware ,  Srikanth Krishnan

    发明人： Ajit Shanware ,  Srikanth Krishnan

    IPC分类号： H01L29/94 ,  G06F17/00 ,  H01L21/66

    CPC分类号： H01L27/092 ,  H01L27/0207

    摘要： An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

    摘要翻译： 集成电路（IC）至少包括第一互补MOS（CMOS）电路，第一CMOS电路包括一个或多个第一n沟道MOS（NMOS）晶体管和一个或多个第一p沟道MOS（PMOS）晶体管，其中 第一NMOS晶体管和第一PMOS晶体管布置在第一CMOS电路中以驱动第一CMOS电路的至少第一公共节点。 第一NMOS晶体管的有效栅极沟道长度的平均值（第一NMOS平均长度）比第一PMOS晶体管的有效栅极沟道长度的平均值（第一PMOS平均长度）至少大2％。