公开(公告)号：US07906405B2

公开(公告)日：2011-03-15

申请号：US12047702

申请日：2008-03-13

申请人： Joe W. McPherson ,  Ajit Shanware

发明人： Joe W. McPherson ,  Ajit Shanware

IPC分类号： H01L21/20

CPC分类号： H01L21/02675 ,  H01G4/33 ,  H01L21/02532 ,  H01L21/02595 ,  H01L28/20 ,  H01L29/94

摘要： Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.

摘要翻译： 与快速热退火和炉退火相比，集成电路的激光扫描退火提供了优点，但是可以在具有多晶硅层的部件​​的区域中引起过热。 公开了分段多晶硅元件以减少过热，以及形成具有段多晶硅元件的部件的方法。

公开(公告)号：US20110165754A1

公开(公告)日：2011-07-07

申请号：US13048463

申请日：2011-03-15

申请人： Joe W. McPherson ,  Ajit Shanware

发明人： Joe W. McPherson ,  Ajit Shanware

IPC分类号： H01L21/02 ,  H01L21/28

CPC分类号： H01L21/02675 ,  H01G4/33 ,  H01L21/02532 ,  H01L21/02595 ,  H01L28/20 ,  H01L29/94

摘要： Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.

摘要翻译： 与快速热退火和炉退火相比，集成电路的激光扫描退火提供了优点，但是可以在具有多晶硅层的部件​​的区域中引起过热。 公开了分段多晶硅元件以减少过热，以及形成具有段多晶硅元件的部件的方法。

公开(公告)号：US20090161290A1

公开(公告)日：2009-06-25

申请号：US12047702

申请日：2008-03-13

申请人： Joe W. McPherson ,  Ajit Shanware

发明人： Joe W. McPherson ,  Ajit Shanware

IPC分类号： H01G4/008 ,  H01L21/20 ,  H01C1/012

CPC分类号： H01L21/02675 ,  H01G4/33 ,  H01L21/02532 ,  H01L21/02595 ,  H01L28/20 ,  H01L29/94

摘要： Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.

摘要翻译： 与快速热退火和炉退火相比，集成电路的激光扫描退火提供了优点，但是可以在具有多晶硅层的部件​​的区域中引起过热。 公开了分段多晶硅元件以减少过热，以及形成具有段多晶硅元件的部件的方法。

公开(公告)号：US07888776B2

公开(公告)日：2011-02-15

申请号：US12165419

申请日：2008-06-30

申请人： Ennis T. Ogawa ,  Honglin Guo ,  Joe W. McPherson

发明人： Ennis T. Ogawa ,  Honglin Guo ,  Joe W. McPherson

IPC分类号： H01L23/544

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00012

摘要： One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.

摘要翻译： 本发明的一个实施例涉及一种划线密封完整性检测器。 在该实施例中，在集成电路芯片芯片中形成划线密封完整性检测器。 划痕密封完整性包括沿集成芯片管芯的周边的至少一部分延伸的划片密封结构和检测器测试结构。 检测器测试结构和划线密封件形成电气系统，其被配置为被访问以监视一个或多个电参数以确定和表征集成电路芯片管芯的划痕密封完整性。 分析电测量的结果以进行统计学相关的可靠性表征。 还公开了其它方法和电路。

公开(公告)号：US20090321734A1

公开(公告)日：2009-12-31

申请号：US12165419

申请日：2008-06-30

申请人： Ennis T. Ogawa ,  Honglin Guo ,  Joe W. McPherson

发明人： Ennis T. Ogawa ,  Honglin Guo ,  Joe W. McPherson

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00012

摘要： One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.

摘要翻译： 本发明的一个实施例涉及一种划线密封完整性检测器。 在该实施例中，在集成电路芯片芯片中形成划线密封完整性检测器。 划痕密封完整性包括沿集成芯片管芯的周边的至少一部分延伸的划片密封结构和检测器测试结构。 检测器测试结构和划线密封件形成电气系统，其被配置为被访问以监视一个或多个电参数以确定和表征集成电路芯片管芯的划痕密封完整性。 分析电测量的结果以进行统计学相关的可靠性表征。 还公开了其它方法和电路。

公开(公告)号：US06965136B2

公开(公告)日：2005-11-15

申请号：US10684617

申请日：2003-10-14

申请人： Yaojian Leng ,  Honglin Guo ,  Joe W. McPherson

发明人： Yaojian Leng ,  Honglin Guo ,  Joe W. McPherson

IPC分类号： H01L21/768 ,  H01L23/552 ,  H01L31/0232

CPC分类号： H01L23/552 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal, 8, (such as copper) that is used to make the interconnect wiring during the semiconductor manufacturing process. The light induced corrosion and re-deposition is caused by the exposure of a P-N junction to light, causing a photovoltaic effect. A photon-blocking layer, 13, is used in the invention to reduce the amount of exposure of the P-N junction to light. The photon blocking layer, 13, of the invention may be a direct band-gap material with a band-gap energy that is less than the lower edge of the energy spectrum of a typical light source used in the semiconductor manufacturing facility (typically less than 1.7 eV).

公开(公告)号：US06737351B2

公开(公告)日：2004-05-18

申请号：US10113504

申请日：2002-04-01

申请人： Ennis T. Ogawa ,  Joe W. McPherson

发明人： Ennis T. Ogawa ,  Joe W. McPherson

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.

公开(公告)号：US5963779A

公开(公告)日：1999-10-05

申请号：US211606

申请日：1998-12-15

申请人： Anthony W. Leigh ,  Joe W. McPherson ,  Kenan J. Dickerson

发明人： Anthony W. Leigh ,  Joe W. McPherson ,  Kenan J. Dickerson

IPC分类号： H01L21/822 ,  G01R31/28 ,  H01L21/66 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L29/78 ,  H01L21/00

CPC分类号： G01R31/2884 ,  G01R31/2856

摘要： Integrated circuit architectures and methods of operation are provided that allow for the connection of a negative back-gate bias voltage to substrate contacts 24, 90, and 56 during burn-in operations. Accordingly, latch up conditions are prevented during burn-in operations when a circuit is especially vulnerable to such conditions and a grounded substrate is provided to allow for the most efficient operation of the circuit during normal conditions.

摘要翻译： 提供集成电路架构和操作方法，其允许在老化操作期间将负的背栅极偏置电压连接到衬底触点24,90和56。 因此，当电路特别容易受到这种情况的影响时，在老化操作期间可以防止闩锁状态，并且提供接地的基板以允许电路在正常状态下的最有效的操作。

公开(公告)号：US4816425A

公开(公告)日：1989-03-28

申请号：US34515

申请日：1987-04-06

申请人： Joe W. McPherson

发明人： Joe W. McPherson

IPC分类号： H01L23/532 ,  H01L29/45 ,  H01L21/283

CPC分类号： H01L29/456 ,  H01L23/53271 ,  H01L2924/0002

摘要： A process for making a semiconductor integrated circuit which has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi.sub.2 or WSi.sub.2. Adhesion of the metal silicide to the polysilicon is enhanced by forming a thin silicon oxide coating on the polysilicon before sputtering the metal silicide. The resulting structure has low resistance but retains the advantages of polysilicon on silicon.

摘要翻译： 一种制造半导体集成电路的方法，该半导体集成电路具有包括多层结构的多层结构的电极，触点和互连，所述多层结构包括多晶硅层和难熔金属硅化物如MoSi 2或WSi 2的上覆层。 通过在溅射金属硅化物之前在多晶硅上形成薄的氧化硅涂层来增强金属硅化物与多晶硅的粘合性。 所得结构具有低电阻，但保留了硅上的多晶硅的优点。

公开(公告)号：US4700215A

公开(公告)日：1987-10-13

申请号：US322797

申请日：1981-11-19

申请人： Joe W. McPherson

发明人： Joe W. McPherson

IPC分类号： H01L23/532 ,  H01L29/45 ,  H01L29/04 ,  H01L23/48 ,  H01L49/02

CPC分类号： H01L29/456 ,  H01L23/53271 ,  H01L2924/0002

摘要： A semiconductor integrated circuit has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi.sub.2 or WSi.sub.2. Adhesion of the metal silicide to the polysilicon is enhanced by forming a thin silicon oxide coating on the polysilicon before sputtering the metal silicide. The resulting structure has low resistance but retains the advantages of polysilicon on silicon.

摘要翻译： 半导体集成电路具有包括多层结构的电极，触点和互连件，该多层结构包括多晶硅层和难熔金属硅化物如MoSi 2或WSi 2的上覆层。 通过在溅射金属硅化物之前在多晶硅上形成薄的氧化硅涂层来增强金属硅化物与多晶硅的粘合性。 所得结构具有低电阻，但保留了硅上的多晶硅的优点。