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1.发明授权Memory interface controller for datum raid operations with a datum multiplier 有权存储器接口控制器，用于使用基准倍数进行基准突袭操作公开(公告)号：US06370616B1
公开(公告)日：2002-04-09
申请号：US09542760
申请日：2000-04-04
IPC分类号： G06F1110
CPC分类号： G06F11/1076 , G06F3/0601 , G06F2003/0692 , G06F2211/1011 , G06F2211/1054
摘要： A memory interface controller employs a DATUM multiplier within a destination address to perform DATUM RAID operations. If destination data is in an XOR memory address space, then the multiplier can indicate to multiply source data by the multiplier and XOR that resulting data with the destination data. The DATUM multiplier can be read in response to detection of a memory command. The multiplier alternatively can be used in connection with an input/output bus write command to write source data from the input/output address space to an XOR memory address space. In response to such a write command, the input/output bus data in the input/output address space is multiplied by the multiplier; that resulting data is XORed with the destination data in the XOR memory address space. The multiplier in this case can be within an input/output bus address associated within the input/output bus data.
摘要翻译： 存储器接口控制器在目的地地址中使用DATUM乘法器来执行DATUM RAID操作。 如果目标数据在XOR存储器地址空间中，则乘法器可以指示乘法器将源数据乘以乘法器，并将所得数据与目标数据进行异或运算。 响应于存储器命令的检测，可以读取DATUM乘法器。 该乘法器可以与输入/输出总线写入命令结合使用，以将源数据从输入/输出地址空间写入XOR存储器地址空间。 响应于这种写入命令，输入/输出地址空间中的输入/输出总线数据乘以乘数; 该结果数据与XOR存储器地址空间中的目标数据进行异或运算。 这种情况下的乘法器可以在输入/输出总线数据内相关的输入/输出总线地址之内。
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公开(公告)号：US20080183906A1
公开(公告)日：2008-07-31
申请号：US11669839
申请日：2007-01-31
IPC分类号： G06F13/10
CPC分类号： G06F13/409 , G06F13/4022
摘要： A method comprises obtaining connectivity information from a plurality of electrical devices. Each such electrical device is separately coupled to a backplane, and at least one electrical device comprises a plurality of electrical interfaces adapted to be selectively coupled to each of multiple other electrical devices. Based on connectivity information from the at least one electrical device, the method further comprises providing configuration information to the at least one electrical device to cause the at least one electrical device to electrically couple to a target other electrical device via the backplane.
摘要翻译： 一种方法包括从多个电气设备获得连接信息。 每个这样的电气设备单独耦合到背板，并且至少一个电气设备包括适于选择性地耦合到多个其他电气设备中的每一个的多个电接口。 基于来自至少一个电气设备的连接信息，所述方法还包括向所述至少一个电气设备提供配置信息以使所述至少一个电气设备经由所述背板电耦合到目标其他电气设备。
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3.发明授权Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data 有权使用读缓冲器和流水线同步DRAM突发读数据对同步DRAM进行RAID XOR操作公开(公告)号：US06370611B1
公开(公告)日：2002-04-09
申请号：US09542624
申请日：2000-04-04
IPC分类号： G06F1216
CPC分类号： G06F11/108 , G06F13/1673 , G06F2211/1054 , G06F2211/1066
摘要： A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.
摘要翻译： 存储器接口控制器包括响应于多个连续的SDRAM突发读取请求的来自同步动态随机存取存储器（DRAM）的流水线数据的读取缓冲器，用于存储写入数据的写入缓冲器，将异或（XOR）引擎转换为XOR 写数据与来自读缓冲器的数据，以及写接口，用于将写数据和从读缓冲器的数据进行异或写入到同步DRAM。 数据在读取缓冲器中被流水线化，通过在将数据从先前的SDRAM突发读取请求传送到同步DRAM之前重复发出SDRAM突发读取请求，直到期望的数据量被存储在读取缓冲器中为止。 因此，存储器接口控制器可以为同步DRAM执行外部读 - 修改 - 写周期。 同步DRAM可以用作RAID（廉价磁盘冗余阵列）内存。
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4.发明授权Memory controller interface with XOR operations on memory read to accelerate RAID operations 有权内存控制器接口通过XOR操作对存储器进行读取，以加速RAID操作公开(公告)号：US06918007B2
公开(公告)日：2005-07-12
申请号：US10237330
申请日：2002-09-09
CPC分类号： G06F11/1076 , G06F2211/1054
摘要： A single read request to a memory controller generates multiple read actions along with XOR/DATUM manipulation of that read data. Fewer memory transfers are required to accomplish a RAID5/DATUM parity update. This allows for higher system performance when memory bandwidth is the limiting system component. In implementation, a read buffer with XOR capability is tightly coupled to a memory controller. New parity does not need to be stored in the controller's memory. Instead, a memory read initiates multiple reads from memory based on an address decode. The data from the reads are multiplied and XOR'd before being returned to the requestor. In the case of a PCI-X requestor, this occurs as a split-completion.
摘要翻译： 对存储器控制器的单个读取请求产生多个读取操作以及该读取数据的XOR / DATUM操作。 需要更少的内存传输来完成RAID 5 / DATUM奇偶校验更新。 当存储器带宽是限制系统组件时，这允许更高的系统性能。 在实现中，具有XOR能力的读缓冲器与存储器控制器紧密耦合。 新奇偶校验不需要存储在控制器的存储器中。 相反，存储器读取基于地址解码来从存储器发起多次读取。 读取的数据在被返回给请求者之前被乘以XOR'd。 在PCI-X请求者的情况下，这是分裂完成。
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公开(公告)号：US07793089B2
公开(公告)日：2010-09-07
申请号：US11669839
申请日：2007-01-31
CPC分类号： G06F13/409 , G06F13/4022
摘要： A method comprises obtaining connectivity information from a plurality of electrical devices. Each such electrical device is separately coupled to a backplane, and at least one electrical device comprises a plurality of electrical interfaces adapted to be selectively coupled to each of multiple other electrical devices. Based on connectivity information from the at least one electrical device, the method further comprises providing configuration information to the at least one electrical device to cause the at least one electrical device to electrically couple to a target other electrical device via the backplane.
摘要翻译： 一种方法包括从多个电气设备获得连接信息。 每个这样的电气设备单独耦合到背板，并且至少一个电气设备包括适于选择性地耦合到多个其他电气设备中的每一个的多个电接口。 基于来自至少一个电气设备的连接信息，所述方法还包括向所述至少一个电气设备提供配置信息以使所述至少一个电气设备经由所述背板电耦合到目标其他电气设备。
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