公开(公告)号：US5285116A

公开(公告)日：1994-02-08

申请号：US573926

申请日：1990-08-28

申请人： Albert Thaik

发明人： Albert Thaik

IPC分类号： H03K17/14 ,  H03K17/16 ,  H03K19/017

CPC分类号： H03K17/145 ,  H03K17/164

摘要： A low-noise high-speed output buffer receives digital control signals for varying the switching delay and di/dt of the buffer. For a plurality of output buffers, one buffer is used to determine the digital control signal values for the rest. The switching delay is controlled by referencing the one output buffer's delay to a clock cycle (e.g., 0.75 T or T, where T equals the clock cycle period). The digital control signal values which define the delay with reference to the clock cycle also determine the di/dt for the output buffers. As process or operating conditions vary, the control signal values change to maintain the delay in the prescribed relation to the clock cycle. Accordingly, the absolute di/dt values change. Thus, the output signal is available by the time needed (e.g., 0.75 T), while the di/dt is varied to an optimum setting based on the absolute delay time. As a result, the variation in di/dt from fastest conditions to slowest conditions is smaller enabling an increased ability to conform to noise margin requirements for increasingly faster systems. Accordingly, a low-noise high-speed output buffer and method of controlling the same is provided.

摘要翻译： 低噪声高速输出缓冲器接收用于改变缓冲器的开关延迟和di / dt的数字控制信号。 对于多个输出缓冲器，使用一个缓冲器来确定其余的数字控制信号值。 通过将一个输出缓冲器的延迟参考到时钟周期（例如，0.75T或T，其中T等于时钟周期周期）来控制开关延迟。 参考时钟周期定义延迟的数字控制信号值也决定了输出缓冲器的di / dt。 随着过程或操作条件的变化，控制信号值发生变化，以保持与时钟周期规定关系的延迟。 因此，绝对di / dt值发生变化。 因此，输出信号可用于所需时间（例如，0.75T），而di / dt基于绝对延迟时间变化到最佳设置。 因此，从最快条件到最慢条件的di / dt的变化较小，能够提高符合越来越快的系统的噪声容限要求的能力。 因此，提供了低噪声高速输出缓冲器及其控制方法。