公开(公告)号：US20070143643A1

公开(公告)日：2007-06-21

申请号：US10561451

申请日：2004-06-17

申请人： Jose Pineda De Gyvez ,  Alexander Gronthoud ,  Rachid Amine

发明人： Jose Pineda De Gyvez ,  Alexander Gronthoud ,  Rachid Amine

IPC分类号： G06F11/00

CPC分类号： G01R31/3008 ,  G01R31/2822 ,  G01R31/3161

摘要： A method and apparatus for testing analogue or RF circuitry, wherein the power supply VDD is ramped up (step 100) and quiescent current measurements are taken at selected values of VDD (step 102) to generate a current signature (step 104). When the power supply is ramped up, all transistors in the circuit pass through several regions of operation, e.g. subthreshold (region A), linear (region B), and saturation (region C). The advantage of transition from region to region is that defects can be detected with distinct accuracy in each of the operating regions. Once the current signature has been generated it can be compared with the current signature of a fault-free device (step 106), to determine (step 108) if the device is operating correctly, and if not, it is discarded.

摘要翻译： 一种用于测试模拟或RF电路的方法和装置，其中电源VDD上升（步骤100），并且在VDD的选定值处进行静态电流测量（步骤102）以产生当前签名（步骤104）。 当电源上升时，电路中的所有晶体管都通过几个操作区域，例如， 亚阈值（区域A），线性（区域B）和饱和度（区域C）。 从区域到区域的转变的优点是可以在每个操作区域中以不同的精度检测缺陷。 一旦生成了当前的签名，就可以将其与无故障设备的当前签名进行比较（步骤106），以确定（步骤108）设备是否正常运行，如果没有，则将其丢弃。

公开(公告)号：US20070132525A1

公开(公告)日：2007-06-14

申请号：US10588939

申请日：2005-01-27

申请人： Jose Pineda de Gyvez ,  Alexander Gronthoud ,  Cristiano Cenci

发明人： Jose Pineda de Gyvez ,  Alexander Gronthoud ,  Cristiano Cenci

IPC分类号： H03L7/099

CPC分类号： H03L7/06 ,  G01R31/2824 ,  G01R31/30 ,  G01R31/3161

摘要： Testing device for testing a phase locked loop having a power supply input, said testing device comprising: a power supply unit for providing a power supply signal VDD having a variation profile to the power supply input of the phase locked loop, wherein a width and height of said variation profile are formed in such a way, that the voltage controlled oscillator is prevented from outputting an oscillating output signal U,,,, ta means for disabling a feedback signal to a phase comparator of the phase locked loop such that said phase locked loop is operated in an open loop mode, and a meter for measuring a measurement signal of the phase locked loop, while said power supply signal is provided to the power supply input.

摘要翻译： 用于测试具有电源输入的锁相环的测试装置，所述测试装置包括：电源单元，用于向所述相的电源输入提供具有变化曲线的电源信号V DD， 锁定回路，其中所述变化曲线的宽度和高度以这样的方式形成，使得压控振荡器被阻止输出振荡输出信号U 1，...， 反馈信号到锁相环的相位比较器，使得所述锁相环以开环模式工作，以及用于测量锁相环的测量信号的仪表，同时所述电源信号被提供给电源 输入。