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公开(公告)号：US20060123368A1
公开(公告)日：2006-06-08
申请号：US10559208
申请日：2004-05-28
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： The present invention relates to real-time adaptive control for best Integrated Circuit (IC) performance. The adaptive behavior is carried out on a local basis. The system is partitioned into different islands (30). Each island (30) is controlled and its working conditions are modified depending on some parameters. The remainder of the chip is controlled as well, depending on other parameters. This requires that each island (30) has a local controller (36) communicating with a global controller (42). The main control parameters are e.g. supply voltage, threshold voltage and clock frequency.
摘要翻译： 本发明涉及用于最佳集成电路（IC）性能的实时自适应控制。 适应行为是在当地进行的。 系统被划分成不同的岛屿（30）。 每个岛（30）被控制，并且其工作条件根据一些参数而被修改。 芯片的其余部分也受到控制，取决于其他参数。 这要求每个岛（30）具有与全局控制器（42）通信的本地控制器（36）。 主要控制参数是例如。 电源电压，阈值电压和时钟频率。
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2.发明申请Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device 有权用于降低状态保持电路，状态保持电路和电子设备中的功耗的方法公开(公告)号：US20060119991A1
公开(公告)日：2006-06-08
申请号：US10525488
申请日：2003-08-04
IPC分类号： H02H7/00
摘要： A method for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising, in an active state, providing a regular power supply (VDD) and a standby power supply (VDD STANDBY) to the state retaining circuit; for a transition from an active state to a standby state, decreasing the regular power supply to ground level and maintaining the standby power supply (VDD STANDBY) thus providing the circuit elements (36, 142, 78, 85) of the state retaining circuit with enough power for retaining the state during standby mode; and for a transition from the standby state to the active state, increasing the regular power supply (VDD) from its ground level to its active level. A circuit for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising a control unit (1) providing at least one control signal; a data input unit (3) providing at least one input signal; a data output unit (7) providing at least one output signal; a data storage unit (5) for holding the state of the circuit during an a standby mode; a regular power supply supplying power to the data storage unit (5) during an active mode; and a standby power supply supplying power to at least a part of the data storage unit (5) during the active mode and the standby mode.
摘要翻译： 公开了一种用于在待机模式期间降低状态保持电路中的功耗的方法，包括：在有源状态下，向状态保持电路提供常规电源（VDD）和待机电源（VDD STANDBY）; 为了从活动状态转变到待机状态，将正常电源降低到接地电平并维持待机电源（VDD STANDBY），从而将状态保持电路的电路元件（36,142,78,85）与 在待机模式下保持状态的足够的电力; 并且为了从待机状态转换到有效状态，将常规电源（VDD）从其地电平增加到其有效电平。 公开了一种用于在备用模式期间降低状态保持电路中的功耗的电路，包括：提供至少一个控制信号的控制单元（1） 提供至少一个输入信号的数据输入单元（3）; 提供至少一个输出信号的数据输出单元（7）; 数据存储单元，用于在待机模式期间保持电路的状态; 在活动模式期间向数据存储单元（5）供电的常规电源; 以及在活动模式和待机模式期间向数据存储单元（5）的至少一部分供电的备用电源。
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公开(公告)号：US20060248354A1
公开(公告)日：2006-11-02
申请号：US10558090
申请日：2004-05-17
IPC分类号： G06F1/00
CPC分类号： H03K19/0016 , H03K19/215
摘要： The present invention relates to an electronic circuit, apparatus and method for monitoring and controlling power consumption. Accordingly, there is provided an electronic circuit, apparatus and method that includes one or more sequential logic elements (12) that are capable of receiving a clock signal (CLK) and an input signal (I) and providing an output signal (O). The sequential logic element (12) further comprises circuitry (20) for monitoring the input and output signals (I, O), and providing a control signal (CS) in response to the input and output signals (I, O), wherein the IC's power consumption is operatively controllable in response to the control signal.
摘要翻译： 本发明涉及用于监视和控制功耗的电子电路，装置和方法。 因此，提供了一种电子电路，装置和方法，其包括能够接收时钟信号（CLK）和输入信号（I）并提供输出信号（O）的一个或多个顺序逻辑元件（12）。 顺序逻辑元件（12）还包括用于监测输入和输出信号（I，O）以及响应于输入和输出信号（I，O）提供控制信号（CS）的电路（20），其中 IC的功耗响应于控制信号而可操作地控制。
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公开(公告)号：US20060190878A1
公开(公告)日：2006-08-24
申请号：US10546395
申请日：2004-02-12
CPC分类号： G06F17/5022 , G06F17/5036
摘要： The present invention relates to a method and circuit arrangement for determining power supply noise of a power distribution network. The power supply noise is determined by measuring the propagation delay of a delay circuit powered by the power distribution network, wherein the result of the measuring step is used as an indicator of the power supply noise. Thereby, a real-time power supply noise monitoring can be carried out at any point of a power distribution network of an observed circuitry.
摘要翻译： 本发明涉及一种用于确定配电网络的电源噪声的方法和电路装置。 通过测量由配电网供电的延迟电路的传播延迟来确定电源噪声，其中测量步骤的结果用作电源噪声的指标。 因此，可以在观察电路的配电网络的任何点处执行实时电源噪声监测。
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公开(公告)号：US20060091941A1
公开(公告)日：2006-05-04
申请号：US10537028
申请日：2003-10-31
IPC分类号： H04B1/10
CPC分类号： H04B15/005
摘要： Sub-circuits of an integrated circuit can act as noise sources on common conductors such as power supply lines and the substrate. Each of these conductors may act as a noise medium capable of transferring noise signals from the noise source to other sub-circuits. One or more feedback circuits are coupled between input and output points on opposite sides of where a circuit to be protected is connected to such a medium, so that a output of the feedback circuit is coupled to the noise medium closer to certain noise sources than the input of the feedback circuit. Preferably, multiple feedback circuits are cross-coupled and have transfer connections so that coupling between the input and outputs of different feedback circuit is at least partially suppressed.
摘要翻译： 集成电路的子电路可以作为诸如电源线和基板的公共导体上的噪声源。 这些导体中的每一个可以用作能够将噪声信号从噪声源传送到其他子电路的噪声介质。 一个或多个反馈电路耦合在其上要被保护的电路连接到这种介质的相对侧的输入和输出点之间，使得反馈电路的输出耦合到更接近特定噪声源的噪声源， 反馈电路的输入。 优选地，多个反馈电路交叉耦合并且具有传输连接，使得不同反馈电路的输入和输出之间的耦合被至少部分地抑制。
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6.发明授权Energy efficient microprocessor platform based on instructional level parallelism 有权基于教学级并行性的节能微处理器平台公开(公告)号：US09009506B2
公开(公告)日：2015-04-14
申请号：US13410247
申请日：2012-03-01
申请人： Hamed Fatemi , Ajay Kapoor , Jose Pineda de Gyvez
发明人： Hamed Fatemi , Ajay Kapoor , Jose Pineda de Gyvez
CPC分类号： G06F9/3836 , G06F1/324 , G06F1/3296 , G06F9/3869 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/22
摘要： Embodiments of a processing architecture are described. The architecture includes a fetch unit for fetching instructions from a data bus. A scheduler receives data from the fetch unit and creates a schedule allocates the data and schedule to a plurality of computational units. The scheduler also modifies voltage and frequency settings of the processing architecture to optimize power consumption and throughput of the system. The computational units include control units and execute units. The control units receive and decode the instructions and send the decoded instructions to execute units. The execute units then execute the instructions according to relevant software.
摘要翻译： 描述处理架构的实施例。 该架构包括用于从数据总线获取指令的提取单元。 调度器从获取单元接收数据并创建调度将数据分配到多个计算单元。 调度器还修改处理架构的电压和频率设置，以优化系统的功耗和吞吐量。 计算单元包括控制单元和执行单元。 控制单元接收和解码指令，并将解码的指令发送到执行单元。 然后执行单元根据相关软件执行指令。
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公开(公告)号：US20070143643A1
公开(公告)日：2007-06-21
申请号：US10561451
申请日：2004-06-17
IPC分类号： G06F11/00
CPC分类号： G01R31/3008 , G01R31/2822 , G01R31/3161
摘要： A method and apparatus for testing analogue or RF circuitry, wherein the power supply VDD is ramped up (step 100) and quiescent current measurements are taken at selected values of VDD (step 102) to generate a current signature (step 104). When the power supply is ramped up, all transistors in the circuit pass through several regions of operation, e.g. subthreshold (region A), linear (region B), and saturation (region C). The advantage of transition from region to region is that defects can be detected with distinct accuracy in each of the operating regions. Once the current signature has been generated it can be compared with the current signature of a fault-free device (step 106), to determine (step 108) if the device is operating correctly, and if not, it is discarded.
摘要翻译： 一种用于测试模拟或RF电路的方法和装置，其中电源VDD上升（步骤100），并且在VDD的选定值处进行静态电流测量（步骤102）以产生当前签名（步骤104）。 当电源上升时，电路中的所有晶体管都通过几个操作区域，例如， 亚阈值（区域A），线性（区域B）和饱和度（区域C）。 从区域到区域的转变的优点是可以在每个操作区域中以不同的精度检测缺陷。 一旦生成了当前的签名，就可以将其与无故障设备的当前签名进行比较（步骤106），以确定（步骤108）设备是否正常运行，如果没有，则将其丢弃。
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公开(公告)号：US20070063690A1
公开(公告)日：2007-03-22
申请号：US10596644
申请日：2004-12-20
申请人： Johannes De Wilde , Jose Pineda De Gyvez , Franciscus De Jong , Josephus Huisken , Hans Boeve , Kim Phan Le
发明人： Johannes De Wilde , Jose Pineda De Gyvez , Franciscus De Jong , Josephus Huisken , Hans Boeve , Kim Phan Le
IPC分类号： G01R15/18
CPC分类号： G01R31/3004 , G01R15/20 , G11C11/16 , G11C11/1673 , G11C11/1675
摘要： A sensor for contactlessly detecting currents, has a sensor element having a magnetic tunnel junction (MTJ), and detection circuitry, the sensor element having a resistance which varies with the magnetic field, and the detection circuitry is arranged to detect a tunnel current flowing through the tunnel junction. The sensor element may share an MTJ stack with memory elements. Also it can provide easy integration with next generation CMOS processes, including MRAM technology, be more compact, and use less power. Solutions for increasing sensitivity of the sensor, such as providing a flux concentrator, and for generating higher magnetic fields with a same current, such as forming L-shaped conductor elements, are given. The greater sensitivity enables less post processing to be used, to save power for applications such as mobile devices. Applications include current sensors, built-in current sensors, and IDDQ and IDDT testing, even for next generation CMOS processes.
摘要翻译： 一种用于非接触式检测电流的传感器，具有传感器元件，具有磁性隧道结（MTJ）和检测电路，传感器元件具有随磁场而变化的电阻，并且检测电路被设置为检测流过的隧道电流 隧道交界处。 传感器元件可以与存储器元件共享MTJ堆叠。 此外，它可以提供与下一代CMOS工艺的轻松集成，包括MRAM技术，更紧凑，更少的功耗。 给出了提高传感器灵敏度的解决方案，例如提供集流器，以及用于产生具有相同电流的较高磁场，例如形成L形导体元件。 更高的灵敏度使得能够使用更少的后处理，以节省诸如移动设备之类的应用的功率。 应用包括电流传感器，内置电流传感器，IDDQ和IDDT测试，甚至适用于下一代CMOS工艺。
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公开(公告)号：US20070132525A1
公开(公告)日：2007-06-14
申请号：US10588939
申请日：2005-01-27
IPC分类号： H03L7/099
CPC分类号： H03L7/06 , G01R31/2824 , G01R31/30 , G01R31/3161
摘要： Testing device for testing a phase locked loop having a power supply input, said testing device comprising: a power supply unit for providing a power supply signal VDD having a variation profile to the power supply input of the phase locked loop, wherein a width and height of said variation profile are formed in such a way, that the voltage controlled oscillator is prevented from outputting an oscillating output signal U,,,, ta means for disabling a feedback signal to a phase comparator of the phase locked loop such that said phase locked loop is operated in an open loop mode, and a meter for measuring a measurement signal of the phase locked loop, while said power supply signal is provided to the power supply input.
摘要翻译： 用于测试具有电源输入的锁相环的测试装置，所述测试装置包括：电源单元，用于向所述相的电源输入提供具有变化曲线的电源信号V DD， 锁定回路，其中所述变化曲线的宽度和高度以这样的方式形成，使得压控振荡器被阻止输出振荡输出信号U 1，...， 反馈信号到锁相环的相位比较器，使得所述锁相环以开环模式工作，以及用于测量锁相环的测量信号的仪表，同时所述电源信号被提供给电源 输入。
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公开(公告)号：US20060187724A1
公开(公告)日：2006-08-24
申请号：US10548340
申请日：2004-03-03
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step 102). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step 104), the bit lines are then shorted together (step 106), the word lines are disabled (step 108) and the bit lines are released (step 110). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step 112). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as “weak” (step 114).
摘要翻译： 一种用于测试静态随机存取存储器（SRAM）阵列以存在弱缺陷的方法和装置。 首先将0/1比率写入存储器阵列（步骤100），然后将位线BL和BLB预充电并均衡到阈值检测电压（步骤102）。 阈值检测电压根据单元的0/1比率编程，以便考虑特定的单元标准和/或特性。 接下来，与阵列中的所有单元相关联的字线基本上同时被启用（步骤104），然后将位线一起短接（步骤106），字线被禁用（步骤108）并且位线被释放 （步骤110）。 按照这些步骤，读取SRAM阵列的内容并将其与原始的0/1比率进行比较（步骤112）。 内容不符合原始0/1比例（即内容已经翻转的内容）的单元格被标记或以其他方式标识为“弱”（步骤114）。
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