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1.发明授权General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software 有权用于解决饱和度问题以验证电路和软件功能的通用数字回溯算法公开(公告)号：US08862439B1
公开(公告)日：2014-10-14
申请号：US12824081
申请日：2010-06-25
CPC分类号： G06F17/504 , G06F17/10
摘要： In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.
摘要翻译： 在本发明的一个实施例中，公开了一种设计验证器，其包括模型提取器和具有算术可满足性求解器的有界模型检验器。 算术可满足性求解器以满足一个或多个数字公式中的每一个的变量的数字数字分配的形式搜索解决方案。 搜索冲突导致一个或多个新的数字公式的推导，用于指导搜索解决方案。 如果搜索找到满足一个或多个数字公式中的每一个的数字分配，则表示系统的功能属性被违反。
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2.发明授权Optimizing integrated circuit design through use of sequential timing information 失效通过使用顺序定时信息优化集成电路设计公开(公告)号：US08589845B2
公开(公告)日：2013-11-19
申请号：US12624395
申请日：2009-11-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
摘要翻译： 提供了一种方法，其包括：确定可用于在电路设计中传播关于关键周期的信号的最小时钟周期; 其中所述关键周期是设计中具有与寄存器数量的延迟成比例最高的周期; 确定电路设计中的电路元件，与电路元件相关联的顺序松弛; 其中所述顺序松弛表示从相应的最大延迟中的最小延迟，所述最大延迟可以基于所确定的对时钟周期持续时间的限制而被添加到所述电路元件是其组成部分的各个结构周期; 使用顺序松弛来确定在设计流程的多个阶段中基于连续优化的设计灵活性。
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公开(公告)号：US07596770B1
公开(公告)日：2009-09-29
申请号：US11144389
申请日：2005-06-02
申请人： Andreas Kuehlmann , Xiaoqun Du
发明人： Andreas Kuehlmann , Xiaoqun Du
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.
摘要翻译： 有限状态机的行为通过将表示有限状态机的组合逻辑行为的过渡关系展开为表示有序状态机在时间序列中的组合逻辑行为的过渡关系序列来表示。 在序列中的过渡关系中确定至少一个状态，其在序列中的后续转变关系中不能达到。 相对于至少一个不可达状态，简化了至少一个状态不能到达的序列中的随后的转变关系。
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公开(公告)号：US07296246B1
公开(公告)日：2007-11-13
申请号：US10701911
申请日：2003-11-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： The present invention provides a process for constrained clock skew scheduling which computes for a given number of clocking domains the optimal phase shifts for the domains and the assignment of the individual registers to the domains. For the within domain latency values, the algorithm can assume a zero-skew clock delivery or apply a user-provided upper bound. Experiments have demonstrated that a constrained clock skew schedule using a few clocking domains combined with small within-domain latency can reliably implement the full sequential optimization potential to date only possible with an unconstrained clock schedule.
摘要翻译： 本发明提供了一种用于约束时钟偏移调度的过程，其针对给定数量的时钟域来计算域的最佳相移以及将各个寄存器分配给域。 对于域内延迟值，该算法可以采用零偏移时钟传递或应用用户提供的上限。 实验已经证明，使用几个时钟域与小的域内延迟结合的约束时钟偏移调度可以可靠地实现迄今为止的完整的顺序优化潜力，只有在无约束时钟调度的情况下才可能。
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公开(公告)号：US08020125B1
公开(公告)日：2011-09-13
申请号：US12208234
申请日：2008-09-10
申请人： Andreas Kuehlmann , Nathan Kitchen
发明人： Andreas Kuehlmann , Nathan Kitchen
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and apparatus for producing a verification of digital circuits is provided. In an exemplary embodiment, a set of Boolean and Integer constraints are derived, and a set of Boolean and Integer stimuli are generated that meet the constraints. These stimuli are then used to verify a digital design, and a verification report is generated. In other example embodiments, a computing apparatus and computer software product are provided. The computer software product containing a set of executable instructions that, when executed, configure the computing apparatus to produce a verification report by the provided methods.
摘要翻译： 提供了一种用于产生数字电路验证的方法和装置。 在示例性实施例中，导出一组布尔和整数约束，并且生成满足约束的一组布尔和整数刺激。 然后利用这些刺激来验证数字设计，并生成验证报告。 在其他示例性实施例中，提供了计算设备和计算机软件产品。 所述计算机软件产品包含一组可执行指令，所述可执行指令在执行时，通过所提供的方法配置所述计算装置以产生验证报告。
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6.发明授权公开(公告)号：US07559040B1
公开(公告)日：2009-07-07
申请号：US11373670
申请日：2006-03-10
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In optimizing a design of an integrated circuit, an iteration of a logic optimization process is performed that at least partially optimizes a circuit design such that there is slack remaining in one or more combinational logic paths in the circuit design following the iteration. A clock latency scheduling process is performed that respectively distributes the remaining slack of one or more respective combinational logic paths in the circuit design across respective registers in the circuit design. Another iteration of the logic optimization process is performed that uses at least a portion of the distributed slack to further optimize the circuit design.
摘要翻译： 在优化集成电路的设计中，执行逻辑优化过程的迭代，其至少部分优化电路设计，使得在迭代之后的电路设计中的一个或多个组合逻辑路径中存在松弛。 执行时钟延迟调度处理，其分别在电路设计中分布在电路设计中的各个寄存器中的一个或多个相应的组合逻辑路径的剩余松弛。 执行逻辑优化过程的另一次迭代，其使用分布式松弛的至少一部分来进一步优化电路设计。
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公开(公告)号：US6035107A
公开(公告)日：2000-03-07
申请号：US919736
申请日：1997-08-28
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A verification technique which is specifically adapted for formally comparing large combinational circuits with some structural similarities. The approach combines the application of Binary Decision Diagrams (BDDs) with circuit graph hashing, automatic insertion of multiple cut frontiers, and a controlled elimination of false negative verification results caused by the cuts. Multiple BDDs are computed for the internal nets of the circuit, originating from the cut frontiers, and the BDD propagation is prioritized by size and discontinued once a given limit is exceeded. The resulting verification engine is reliably accurate and efficient for a wide variety of practical hardware designs ranging from identical circuits to designs with very few similarities.
摘要翻译： 一种特别适用于正式比较大组合电路与一些结构相似性的验证技术。 该方法结合了二进制决策图（BDD）与电路图散列的应用，自动插入多个切割边界，以及控制消除由切割引起的假否定验证结果。 对于源自切割边界的电路的内部网络计算多个BDD，并且BDD传播由大小确定优先级，并且一旦超过给定限制就停止。 所得到的验证引擎对于从相同的电路到非常少的相似性的设计的各种各样的实际硬件设计是可靠的准确和有效的。
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8.发明授权CMOS transistor network to gate level model extractor for simulation, verification and test generation 失效CMOS晶体管网络到门级模型提取器进行仿真，验证和测试生成
公开(公告)号：US5629858A
公开(公告)日：1997-05-13
申请号：US406283
申请日：1995-03-17
IPC分类号： G01R31/3183 , G06F17/50
CPC分类号： G01R31/318357 , G06F17/5022
摘要： A technique for extracting a gate level logic model from transistor networks has been described. The resultant logic model can be technology dependent or technology independent, depending on control parameters and environment of the program. It handles all CMOS logic families including static, precharge, pass CMOS switching network and self-resetting families. The output gate level model can be used in variety of applications including but not limited to logic simulation, verification, test generation, debug, diagnosis, etc.
摘要翻译： 已经描述了从晶体管网络提取门级逻辑模型的技术。 结果逻辑模型可以依赖于技术或与技术无关，具体取决于程序的控制参数和环境。 它处理所有CMOS逻辑系列，包括静态，预充电，通过CMOS开关网络和自复位系列。 输出门级模型可用于各种应用，包括但不限于逻辑仿真，验证，测试生成，调试，诊断等。
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9.发明授权Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software 失效具有通用数字回溯算法的装置，用于解决满足性问题以验证电路和软件的功能公开(公告)号：US08656330B1
公开(公告)日：2014-02-18
申请号：US12970851
申请日：2010-12-16
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/10
摘要： In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.
摘要翻译： 在本发明的一个实施例中，公开了一种设计验证器，其包括模型提取器和具有算术可满足性求解器的有界模型检验器。 算术可满足性求解器以满足一个或多个数字公式中的每一个的变量的数字数字分配的形式搜索解决方案。 搜索冲突导致一个或多个新的数字公式的推导，用于指导搜索解决方案。 如果搜索找到满足一个或多个数字公式中的每一个的数字分配，则表示系统的功能属性被违反。
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公开(公告)号：US08418101B1
公开(公告)日：2013-04-09
申请号：US13020491
申请日：2011-02-03
申请人： Andreas Kuehlmann , Xiaoqun Du
发明人： Andreas Kuehlmann , Xiaoqun Du
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.
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