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1.发明授权Optimizing integrated circuit design through use of sequential timing information 失效通过使用顺序定时信息优化集成电路设计公开(公告)号：US08589845B2
公开(公告)日：2013-11-19
申请号：US12624395
申请日：2009-11-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
摘要翻译： 提供了一种方法，其包括：确定可用于在电路设计中传播关于关键周期的信号的最小时钟周期; 其中所述关键周期是设计中具有与寄存器数量的延迟成比例最高的周期; 确定电路设计中的电路元件，与电路元件相关联的顺序松弛; 其中所述顺序松弛表示从相应的最大延迟中的最小延迟，所述最大延迟可以基于所确定的对时钟周期持续时间的限制而被添加到所述电路元件是其组成部分的各个结构周期; 使用顺序松弛来确定在设计流程的多个阶段中基于连续优化的设计灵活性。
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公开(公告)号：US07296246B1
公开(公告)日：2007-11-13
申请号：US10701911
申请日：2003-11-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： The present invention provides a process for constrained clock skew scheduling which computes for a given number of clocking domains the optimal phase shifts for the domains and the assignment of the individual registers to the domains. For the within domain latency values, the algorithm can assume a zero-skew clock delivery or apply a user-provided upper bound. Experiments have demonstrated that a constrained clock skew schedule using a few clocking domains combined with small within-domain latency can reliably implement the full sequential optimization potential to date only possible with an unconstrained clock schedule.
摘要翻译： 本发明提供了一种用于约束时钟偏移调度的过程，其针对给定数量的时钟域来计算域的最佳相移以及将各个寄存器分配给域。 对于域内延迟值，该算法可以采用零偏移时钟传递或应用用户提供的上限。 实验已经证明，使用几个时钟域与小的域内延迟结合的约束时钟偏移调度可以可靠地实现迄今为止的完整的顺序优化潜力，只有在无约束时钟调度的情况下才可能。
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3.发明授权Reducing critical cycle delay in an integrated circuit design through use of sequential slack 失效通过使用顺序松弛减少集成电路设计中的关键周期延迟公开(公告)号：US07913210B2
公开(公告)日：2011-03-22
申请号：US11743326
申请日：2007-05-02
IPC分类号： G06F9/455
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
摘要翻译： 提供了一种方法，其包括：确定可用于在电路设计中传播关于关键周期的信号的最小时钟周期; 其中所述关键周期是设计中具有与寄存器数量的延迟成比例最高的周期; 确定电路设计中的电路元件，与电路元件相关联的顺序松弛; 其中所述顺序松弛表示从相应的最大延迟中的最小延迟，所述最大延迟可以基于所确定的对时钟周期持续时间的限制而被添加到所述电路元件是其组成部分的各个结构周期; 使用顺序松弛来确定在设计流程的多个阶段中基于连续优化的设计灵活性。
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4.发明授权Data path and placement optimization in an integrated circuit through use of sequential timing information 失效通过使用顺序定时信息，集成电路中的数据路径和布局优化公开(公告)号：US07624364B2
公开(公告)日：2009-11-24
申请号：US11743356
申请日：2007-05-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
摘要翻译： 提供了一种方法，其包括：确定可用于在电路设计中传播关于关键周期的信号的最小时钟周期; 其中所述关键周期是设计中具有与寄存器数量的延迟成比例最高的周期; 确定电路设计中的电路元件，与电路元件相关联的顺序松弛; 其中所述顺序松弛表示从相应的最大延迟中的最小延迟，所述最大延迟可以基于所确定的对时钟周期持续时间的限制而被添加到所述电路元件是其组成部分的各个结构周期; 使用顺序松弛来确定在设计流程的多个阶段中基于连续优化的设计灵活性。
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5.发明申请Optimizing integrated circuit design through use of sequential timing information 失效通过使用顺序定时信息优化集成电路设计公开(公告)号：US20080276210A1
公开(公告)日：2008-11-06
申请号：US11743356
申请日：2007-05-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
摘要翻译： 提供了一种方法，其包括：确定可用于在电路设计中传播关于关键周期的信号的最小时钟周期; 其中所述关键周期是设计中具有与寄存器数量的延迟成比例最高的周期; 确定电路设计中的电路元件，与电路元件相关联的顺序松弛; 其中所述顺序松弛表示从相应的最大延迟中的最小延迟，所述最大延迟可以基于所确定的对时钟周期持续时间的限制而被添加到所述电路元件是其组成部分的各个结构周期; 使用顺序松弛来确定在设计流程的多个阶段中基于连续优化的设计灵活性。
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公开(公告)号：US20080276209A1
公开(公告)日：2008-11-06
申请号：US11743326
申请日：2007-05-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
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7.发明授权Reducing critical cycle delay in an integrated circuit design through use of sequential slack 失效通过使用顺序松弛减少集成电路设计中的关键周期延迟公开(公告)号：US08307316B2
公开(公告)日：2012-11-06
申请号：US13053044
申请日：2011-03-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
摘要翻译： 提供了一种方法，其包括：确定可用于在电路设计中传播关于关键周期的信号的最小时钟周期; 其中所述关键周期是设计中具有与寄存器数量的延迟成比例最高的周期; 确定电路设计中的电路元件，与电路元件相关联的顺序松弛; 其中所述顺序松弛表示从相应的最大延迟中的最小延迟，所述最大延迟可以基于所确定的对时钟周期持续时间的限制而被添加到所述电路元件是其组成部分的各个结构周期; 使用顺序松弛来确定在设计流程的多个阶段中基于连续优化的设计灵活性。
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8.发明授权Optimizing integrated circuit design through use of sequential timing information 失效通过使用顺序定时信息优化集成电路设计公开(公告)号：US07743354B2
公开(公告)日：2010-06-22
申请号：US11743301
申请日：2007-05-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
摘要翻译： 提供了一种方法，其包括：确定可用于在电路设计中传播关于关键周期的信号的最小时钟周期; 其中所述关键周期是设计中具有与寄存器数量的延迟成比例最高的周期; 确定电路设计中的电路元件，与电路元件相关联的顺序松弛; 其中所述顺序松弛表示从相应的最大延迟中的最小延迟，所述最大延迟可以基于所确定的对时钟周期持续时间的限制而被添加到所述电路元件是其组成部分的各个结构周期; 使用顺序松弛来确定在设计流程的多个阶段中基于连续优化的设计灵活性。
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9.发明申请OPTIMIZING INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL TIMING INFORMATION 失效通过使用顺序时序信息优化集成电路设计公开(公告)号：US20100115477A1
公开(公告)日：2010-05-06
申请号：US12624395
申请日：2009-11-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
摘要翻译： 提供了一种方法，其包括：确定可用于在电路设计中传播关于关键周期的信号的最小时钟周期; 其中所述关键周期是设计中具有与寄存器数量的延迟成比例最高的周期; 确定电路设计中的电路元件，与电路元件相关联的顺序松弛; 其中所述顺序松弛表示从相应的最大延迟中的最小延迟，所述最大延迟可以基于所确定的对时钟周期持续时间的限制而被添加到所述电路元件是其组成部分的各个结构周期; 使用顺序松弛来确定在设计流程的多个阶段中基于连续优化的设计灵活性。
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10.发明申请REDUCING CRITICAL CYCLE DELAY IN AN INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL SLACK 失效通过使用顺序滑块减少集成电路设计中的关键周期延迟公开(公告)号：US20110252389A1
公开(公告)日：2011-10-13
申请号：US13053044
申请日：2011-03-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to as certain sequential optimization based design flexibility throughout multiple stages of a design flow.
摘要翻译： 提供了一种方法，其包括：确定可用于在电路设计中传播关于关键周期的信号的最小时钟周期; 其中所述关键周期是设计中具有与寄存器数量的延迟成比例最高的周期; 确定电路设计中的电路元件，与电路元件相关联的顺序松弛; 其中所述顺序松弛表示从相应的最大延迟中的最小延迟，所述最大延迟可以基于所确定的对时钟周期持续时间的限制而被添加到所述电路元件是其组成部分的各个结构周期; 在设计流程的多个阶段使用顺序松弛作为某种顺序优化设计灵活性。
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