公开(公告)号：US4290051A

公开(公告)日：1981-09-15

申请号：US62175

申请日：1979-07-30

申请人： Alexei P. Stakhov ,  Andrei A. Kozak ,  Nikolai A. Solyanichenko ,  Ivan V. Kuzmin ,  Alexei D. Azarov

发明人： Alexei P. Stakhov ,  Andrei A. Kozak ,  Nikolai A. Solyanichenko ,  Ivan V. Kuzmin ,  Alexei D. Azarov

IPC分类号： H03M7/00 ,  H03K13/24

CPC分类号： H03M7/001

摘要： A device for reducing irrational-base codes to a minimal form, comprising "n" identical functional cells whereof each Bth cell incorporates a flip-flop with a count input and an AND convolution element intended to evaluate the possibility of performing the operation of convoluting the (B-1)th and (B-p-1)th code digits to the Bth code digit. One of the inputs of the AND convolution element is connected to an inverting output of the flip-flop whose direct output serves as an information output of the Bth functional cell. The flip-flop has its set, reset and count inputs connected to an information input, a convolution set input and an inversion signal input, respectively, of the Bth functional cell, the inversion signal input being connected to an information output of the (B-1)th functional cell. The remaining inputs of the AND convolution element are a first convolution signal input, a second convolution signal input and a convolution control input of the Bth functional cell. An output of the AND convolution element is a convolution signal output of the Bth functional cell, which output is respectively connected to a first convolution signal input and a second convolution signal input of the (B-1)th and (B-p-1)th functional cells.

摘要翻译： 一种用于将非理性基础代码减少到最小形式的装置，包括“n”个相同的功能单元，其中每个第B个单元包括具有计数输入的触发器和用于评估执行卷积运算的操作的可能性的AND卷积单元 （B-1）和（Bp-1）个码位数。 AND卷积单元的输入之一连接到触发器的反相输出，其直接输出用作B功能单元的信息输出。 触发器具有分别连接到B功能单元的信息输入，卷积设置输入和反相信号输入的设定，复位和计数输入，反相信号输入连接到（B -1）功能细胞。 AND卷积单元的剩余输入是第B卷函数单元的第一卷积信号输入，第二卷积信号输入和卷积控制输入。 AND卷积单元的输出是B功能单元的卷积信号输出，该输出分别连接到第（B-1）和（B-1）th的第一卷积信号输入和第二卷积信号输入 功能细胞。

公开(公告)号：US4276608A

公开(公告)日：1981-06-30

申请号：US38930

申请日：1979-05-14

申请人： Alexei P. Stakhov ,  Nikolai A. Solyanichenko ,  Vladimir A. Luzheisky ,  Alexandr V. Ovodenko ,  Andrei A. Kozak

发明人： Alexei P. Stakhov ,  Nikolai A. Solyanichenko ,  Vladimir A. Luzheisky ,  Alexandr V. Ovodenko ,  Andrei A. Kozak

IPC分类号： G06F7/49 ,  G06F7/60 ,  G06F7/72

CPC分类号： G06F7/60

摘要： A Fibonacci p-code parallel adder comprises an augend register and an addend register having outputs coupled to the inputs of an end-of-addition detector and a monitoring unit and to the data inputs of a logic unit which comprises n rewrite AND gates. The AND gates have their inputs coupled to the complement and true outputs respectively of the augend and addend registers so as to provide for analyzing the condition of the flip-flips of the registers, and have their outputs coupled to the set inputs of the bit positions of the augend register and, via a delay unit, to the reset inputs of the bit position of the addend register, which provides for transfer of a 1 from the ith bit position of the addend register to the ith bit position of the augend register containing a 0. A Fibonnaci p-code minimizing unit has its inputs coupled to the outputs of the augend and addend registers, and has its outputs coupled to the normalize signal input of the augend register. This allows for the reduction of the codeword contained in the augend register to the minimal form with the codeword contained in the addend register being taken into consideration.

摘要翻译： 斐波那契P代码并行加法器包括加法寄存器和加法寄存器，其具有耦合到加法终止检测器和监视单元的输入的输出以及包括n个重写与门的逻辑单元的数据输入。 AND门的输入分别与加法寄存器和加法寄存器的补码和真实输出相连，以便分析寄存器翻盖的条件，并将其输出耦合到位位置的设定输入 的加法寄存器，并且通过延迟单元到加法寄存器的位位置的复位输入，该复位输入提供从加法寄存器的第i位位置将1传送到加法寄存器的第i位位置，其包含 一个Fibonnaci p代码最小化单元的输入耦合到加法寄存器和加法寄存器的输出，并且其输出耦合到加法寄存器的归一化信号输入。 这允许将包含在加法寄存器中的代码字减少到最小形式，同时考虑加法寄存器中包含的代码字。