公开(公告)号：US4037196A

公开(公告)日：1977-07-19

申请号：US759582

申请日：1977-01-14

申请人： Steven B. Atkinson ,  James E. Reed

发明人： Steven B. Atkinson ,  James E. Reed

IPC分类号： F16H59/70 ,  F16H63/42 ,  G09G3/14 ,  H03M7/00 ,  B60Q1/26

CPC分类号： F16H63/42 ,  F16H59/70 ,  G09G3/14 ,  H03M7/001 ,  Y10T307/76

摘要： An apparatus for indicating the position of a gearshift mechanism of a transmission which includes a plurality of forward-speed shift bars contained in and movable within a transmission housing; a number of microswitches are mounted in the housing for selective engagement by the shift bars. The microswitches feed a coding device which generates unique binary codes depending upon the microswitch or switches engaged by the shift bars when the latter are moved into position by a gearshift selector lever, for engaging one of a number of gears of the multiple gear transmission. The binary coded signals are decoded in a decoder/driver which in turn is connected to a digital display device for numerically displaying the selected gear.

摘要翻译： 一种用于指示变速箱换挡机构的位置的装置，其包括容纳在变速器壳体内并在变速器壳体内可移动的多个前进变速杆; 许多微型开关安装在壳体中，用于由换档杆选择性地接合。 微型开关馈送编码装置，该编码装置根据微型开关或变速杆所接合的开关，当变速杆通过换档换档杆移动到位置时，产生独特的二进制代码，用于接合多档传动装置的多个档位之一。 二进制编码信号在解码器/驱动器中解码，该解码器/驱动器又连接到用于数字显示所选择的档位的数字显示装置。

公开(公告)号：US4027174A

公开(公告)日：1977-05-31

申请号：US701125

申请日：1976-06-30

申请人： Yoshihiro Ogata

发明人： Yoshihiro Ogata

IPC分类号： G11C11/413 ,  G11C8/10 ,  H03K19/017 ,  H03K19/096 ,  H03M7/00 ,  H03K19/08 ,  G11C8/00 ,  G11C15/04 ,  H03K19/34

CPC分类号： H03M7/001 ,  G11C8/10 ,  H03K19/017 ,  H03K19/01728 ,  H03K19/0963

摘要： A dynamic decoder circuit including at least first, second and third complementary MOS transistor circuits designed to minimize power consumption and able to produce high output signal levels. The first circuit comprises a first MOS transistor of a first channel type and a plurality of second MOS transistors of a second channel type having the drains thereof connected to that of the first MOS transistor, wherein address signal or signals are selectively applied to the gates of the second MOS transistors and a first timing signal is imparted to the gate of the first MOS transistor. The second circuit comprises a third MOS transistor of the second channel type and a fourth MOS transistor of the first channel type having the drain thereof connected to that of the third MOS transistor, the gate of the third MOS transistor being coupled to the connection point between the drain of said first transistor and those of the second MOS transistors, wherein said first timing signal is imparted to the gate of the fourth MOS transistor and a second timing signal is applied to the source of the third MOS transistor. The third circuit comprises a fifth MOS transistor of the first channel type and a sixth MOS transistor of the second channel type having the drain thereof connected to that of the fifth MOS transistor, the gate of the fifth MOS transistor being coupled to the connection point between the drain of the third MOS transistor and that of the fourth MOS transistor, wherein a third timing signal is imparted to the gate of the sixth MOS transistor, and the output of the decoder circuit is available at the connection point between the drain of the fifth MOS transistor and that of the sixth MOS transistor.

摘要翻译： 一种动态解码器电路，包括至少第一，第二和第三互补MOS晶体管电路，其被设计为最小化功耗并能够产生高输出信号电平。 第一电路包括第一沟道类型的第一MOS晶体管和第二沟道类型的多个第二MOS晶体管，其第二沟道类型的第二MOS晶体管的漏极连接到第一MOS晶体管的漏极，其中地址信号或信号被选择性地施加到栅极 第二MOS晶体管和第一定时信号被施加到第一MOS晶体管的栅极。 第二电路包括第二沟道型的第三MOS晶体管和第一沟道型的第四MOS晶体管，其漏极连接到第三MOS晶体管的漏极，第三MOS晶体管的栅极耦合到第三MOS晶体管之间的连接点 所述第一晶体管的漏极和第二MOS晶体管的漏极，其中所述第一定时信号被施加到第四MOS晶体管的栅极，并且第二定时信号被施加到第三MOS晶体管的源极。 第三电路包括第一通道类型的第五MOS晶体管和第二沟道类型的第六MOS晶体管，其漏极连接到第五MOS晶体管的漏极，第五MOS晶体管的栅极耦合到第五MOS晶体管之间的连接点 第三MOS晶体管的漏极和第四MOS晶体管的漏极，其中第三定时信号被施加到第六MOS晶体管的栅极，并且解码器电路的输出可在第五MOS晶体管的漏极之间的连接点处获得 MOS晶体管和第六MOS晶体管。

公开(公告)号：US4093942A

公开(公告)日：1978-06-06

申请号：US693121

申请日：1976-06-04

申请人： Yasoji Suzuki ,  Yoshio Kaneko ,  Yoshihisa Shiotari

发明人： Yasoji Suzuki ,  Yoshio Kaneko ,  Yoshihisa Shiotari

IPC分类号： G11C17/08 ,  G11C17/12 ,  H03M7/00 ,  H04Q3/52 ,  H04Q3/00

CPC分类号： G11C17/12 ,  G11C17/08 ,  H03M7/001 ,  H04Q3/521

摘要： A matrix circuit acting as a read only memory (ROM) comprises first and second groups of input lines, a third group of input lines arranged between the first and second groups of input lines, a plurality of groups of output lines intersecting the input lines off the first, second and third group, each group of the output lines having one terminal commonly connected in a wired OR fasion to one end of a power source and having the other terminal commonly connected to the ground. A plurality of first switching elements are respectively connected to the output lines and selectively driven by an input signal supplied to the first group of the input lines, a plurality of second switching elements driven by the same input signal as that supplied to the first switching elements and respectively connected to the output lines each lying adjacent to the output lines connected with the first switching elements, and a plurality of third switching elements respectively connected between the adjacent output lines and selectively driven by an input signal supplied to the third group of input lines.

摘要翻译： 用作只读存储器（ROM）的矩阵电路包括第一和第二组输入线，布置在第一和第二组输入线之间的第三组输入线，与输入线相交的多组输出线 第一组，第二组和第三组，每组输出线具有一个端子共同连接到电源的一端的有线OR，并且另一个端子共同连接到地。 多个第一开关元件分别连接到输出线并且选择性地由提供给第一组输入线的输入信号驱动，多个第二开关元件由与提供给第一开关元件的输入信号相同的输入信号驱动的多个第二开关元件 并且分别连接到各自邻近与第一开关元件连接的输出线的输出线，以及分别连接在相邻输出线之间并由提供给第三组输入线的输入信号选择性驱动的多个第三开关元件 。

公开(公告)号：US4051457A

公开(公告)日：1977-09-27

申请号：US655139

申请日：1976-02-03

申请人： Fumiyuki Inose ,  Kenji Fujikata ,  Norio Yokozawa

发明人： Fumiyuki Inose ,  Kenji Fujikata ,  Norio Yokozawa

IPC分类号： G11B20/00 ,  G06F3/153 ,  G06K15/10 ,  G09G1/02 ,  G09G5/24 ,  H03M7/00 ,  G11C15/00

CPC分类号： H03M7/001 ,  G09G1/02

摘要： In a character displaying device having a character pattern memory which is made up of a circulating sequential access memory storing character patterns therein, a character pattern generating system comprises a high speed buffer memory which stores the character codes of one line or any other suitable amount of characters to be displayed and the corresponding character patterns, so that each time one character is delivered as an output from the character pattern memory, the presence of the character code of the particular character is examined for all the character codes of the buffer memory, and the character pattern of the particular character is written into the buffer memory when the character codes are coincident, the writing operations being sequentially executed in the order of the character outputs of the character pattern memory, thereby making it possible to finish all the character patterns in the buffer memory within a period in which the read-out of the character pattern memory circulates.

公开(公告)号：US4029970A

公开(公告)日：1977-06-14

申请号：US629259

申请日：1975-11-06

申请人： Se J. Hong ,  Daniel L. Ostapko

发明人： Se J. Hong ,  Daniel L. Ostapko

IPC分类号： H03K19/177 ,  H03M7/00 ,  H03K19/20 ,  G06F9/00 ,  H03K13/00

CPC分类号： H03K19/17708 ,  H03M7/001

摘要： This specification describes a decoder for a programmable logic array (PLA) having opposite ends of input lines of the array connected to outputs of different decoders. Previously two-bit decoders were arranged on opposite sides of the array to generate input variables from two sets of two different input signals each and feed those input variables to four input lines. Here, instead of using two-bit decoders, four one-bit decoders are positioned on each side. The outputs of these one-bit decoders are programmable to change the connections between them and the input lines of the array. The arrangement permits the decoders to perform one-bit, two-bit decoding on signals on the same side of the input lines, to do two-bit decoding on signals on opposite sides of the array and in combination with other sets of decoders to do three and four-bit decoding of input signals.

摘要翻译： 本说明书描述了用于可编程逻辑阵列（PLA）的解码器，其具有连接到不同解码器的输出的阵列的输入线的相对端。 以前在阵列的相对侧布置了两位解码器，以从两组两个不同的输入信号中产生输入变量，并将这些输入变量馈送到四条输入线。 这里，代替使用两位解码器，在每一侧定位四个一位解码器。 这些一位解码器的输出可编程为改变它们与阵列的输入线之间的连接。 该布置允许解码器对输入线的同一侧上的信号执行一比特的两比特解码，对阵列的相对侧上的信号进行两位解码，并结合其他解码器组来实现 输入信号的三位和四位解码。

公开(公告)号：US4011549A

公开(公告)日：1977-03-08

申请号：US609855

申请日：1975-09-02

申请人： Alan Richard Bormann

发明人： Alan Richard Bormann

IPC分类号： G11C8/08 ,  H03K19/096 ,  H03M7/00 ,  G11C11/44

CPC分类号： H03K19/096 ,  G11C8/08 ,  H03M7/001

摘要： A decoder for a semiconductor MOS random access memory includes a dynamic NOR gate having a first output. The decoder also includes a selection MOSFET for providing a selection signal to a selection conductor connected to a row or column of an array of storage cells of said random access memory. The gate electrode of the selection MOSFET is connected to the output node of the NOR gate. The drain of the selection MOSFET is connected to a signal conductor adapted to having a signal applied thereto which is a function of a read/write signal applied to said random access memory. The source of the selection MOSFET is connected to the selection conductor. A feedback MOSFET is coupled between the output of the dynamic NOR gate and the selection conductor and has its gate electrode controlled by the signal which is a function of the read/write input signal. When the NOR gate is selected by a particular combination of address input variables, its initially precharged output node is discharged to ground. The feedback MOSFET discharges the selection conductor to ground through the feedback MOSFET and the combination of input MOSFETs of the NOR gate which previously discharged the output node thereof. The discharge of the selection conductor occurs when the read selection signal is applied to the gate of the feedback MOSFET.

摘要翻译： 用于半导体MOS随机存取存储器的解码器包括具有第一输出的动态或非门。 解码器还包括选择MOSFET，用于向连接到所述随机存取存储器的存储单元阵列的行或列的选择导体提供选择信号。 选择MOSFET的栅电极连接到或非门的输出节点。 选择MOSFET的漏极连接到适于施加到其上的信号的信号导体，其是施加到所述随机存取存储器的读/写信号的函数。 选择MOSFET的源极连接到选择导体。 反馈MOSFET耦合在动态NOR门的输出和选择导体之间，并且其栅电极由作为读/写输入信号的函数的信号控制。 当NOR门由地址输入变量的特定组合选择时，其初始预充电输出节点被放电到地。 反馈MOSFET通过反馈MOSFET和预先对其输出节点放电的或非门的输入MOSFET的组合将选择导体放电到地。 当读选择信号被施加到反馈MOSFET的栅极时，选择导体的放电发生。

公开(公告)号：US4290051A

公开(公告)日：1981-09-15

申请号：US62175

申请日：1979-07-30

申请人： Alexei P. Stakhov ,  Andrei A. Kozak ,  Nikolai A. Solyanichenko ,  Ivan V. Kuzmin ,  Alexei D. Azarov

发明人： Alexei P. Stakhov ,  Andrei A. Kozak ,  Nikolai A. Solyanichenko ,  Ivan V. Kuzmin ,  Alexei D. Azarov

IPC分类号： H03M7/00 ,  H03K13/24

CPC分类号： H03M7/001

摘要： A device for reducing irrational-base codes to a minimal form, comprising "n" identical functional cells whereof each Bth cell incorporates a flip-flop with a count input and an AND convolution element intended to evaluate the possibility of performing the operation of convoluting the (B-1)th and (B-p-1)th code digits to the Bth code digit. One of the inputs of the AND convolution element is connected to an inverting output of the flip-flop whose direct output serves as an information output of the Bth functional cell. The flip-flop has its set, reset and count inputs connected to an information input, a convolution set input and an inversion signal input, respectively, of the Bth functional cell, the inversion signal input being connected to an information output of the (B-1)th functional cell. The remaining inputs of the AND convolution element are a first convolution signal input, a second convolution signal input and a convolution control input of the Bth functional cell. An output of the AND convolution element is a convolution signal output of the Bth functional cell, which output is respectively connected to a first convolution signal input and a second convolution signal input of the (B-1)th and (B-p-1)th functional cells.

摘要翻译： 一种用于将非理性基础代码减少到最小形式的装置，包括“n”个相同的功能单元，其中每个第B个单元包括具有计数输入的触发器和用于评估执行卷积运算的操作的可能性的AND卷积单元 （B-1）和（Bp-1）个码位数。 AND卷积单元的输入之一连接到触发器的反相输出，其直接输出用作B功能单元的信息输出。 触发器具有分别连接到B功能单元的信息输入，卷积设置输入和反相信号输入的设定，复位和计数输入，反相信号输入连接到（B -1）功能细胞。 AND卷积单元的剩余输入是第B卷函数单元的第一卷积信号输入，第二卷积信号输入和卷积控制输入。 AND卷积单元的输出是B功能单元的卷积信号输出，该输出分别连接到第（B-1）和（B-1）th的第一卷积信号输入和第二卷积信号输入 功能细胞。

公开(公告)号：US4190897A

公开(公告)日：1980-02-26

申请号：US783516

申请日：1977-04-01

申请人： Ashok H. Someshwar

发明人： Ashok H. Someshwar

IPC分类号： G11C17/12 ,  H03M7/00 ,  G11C8/00 ,  G11C17/00

CPC分类号： H03M7/001 ,  G11C17/12

摘要： A Read-Only-Memory (ROM) is addressed with a binary coded decimal (BCD) address in an address register or program counter. The ROM comprises an array of memory cells with associated row and column lines for addressing the array. Row and column decoders responsive to the address in the address register identify a unique row and column line for each BCD address. The row and column decoders comprise a plurality of decoders in cascaded levels. The decorders in any given level decode particular bits of the address in the address register; these decoders decode a one-out-of-a-prime-number, which prime number is a factor of the number of memory locations in the array.

摘要翻译： 只读存储器（ROM）在地址寄存器或程序计数器中用二进制编码十进制（BCD）地址寻址。 ROM包括具有用于寻址阵列的相关联的行和列线的存储器单元的阵列。 响应地址寄存器中的地址的行和列解码器为每个BCD地址标识唯一的行和列线。 行和列解码器包括级联级的多个解码器。 任何给定级别的解码对地址寄存器中的地址的特定位进行解码; 这些解码器解码一个一个素数，这个素数是数组中存储单元数量的一个因素。

公开(公告)号：US4190893A

公开(公告)日：1980-02-26

申请号：US852445

申请日：1977-11-17

申请人： Daniel D. Gajski

发明人： Daniel D. Gajski

IPC分类号： H03M7/18 ,  G06F7/00 ,  G06F7/38 ,  G06F7/72 ,  H03M7/00 ,  H03M13/00 ,  G06F7/48 ,  G06F7/50

CPC分类号： H03M7/001 ,  G06F7/727

摘要： A modular modulo 3 module is provided having a plurality of input terminals for receiving in parallel two bytes of numerical data, and a plurality of output terminals for outputting the modulo 3 residue of each byte of data individually and the modulo 3 residue of the sum of the input bytes. The modulo 3 module is implemented through a plurality of first type modules which combine logically the numerical data on individual pairs of inputs and feed in turn a logrithmic array of second type modules which combine logically to generate the modulo 3 outputs.

摘要翻译： 提供模块化模3模块，其具有用于并行地并行接收数字数据的多个输入端子和用于单独输出每个字节数据的模3残差的多个输出端子， 输入字节。 模3模块通过多个第一类型模块来实现，该多个第一类型模块逻辑地组合各个输入对的数字数据，并依次馈送第二类型模块的逻辑阵列，其逻辑组合以产生模3输出。

公开(公告)号：US4055841A

公开(公告)日：1977-10-25

申请号：US665332

申请日：1976-03-09

申请人： Charles David Crawford

发明人： Charles David Crawford

IPC分类号： H03M7/00 ,  H03K13/24

CPC分类号： H03M7/001

摘要： Signals representative of information bits are converted from one binary code, for example, Gray code, to another binary code, for example, conventional binary, and vice versa, by advantageously employing optical couplers in conjunction with buffer amplifiers. The optical couplers include light emitting diodes and associated phototransistors which are uniquely connected in circuit relationship with the outputs of the buffer amplifiers to effect the desired code conversions.

摘要翻译： 通过有利地使用光耦合器与缓冲放大器相结合，代表信息位的信号从一个二进制码（例如，格雷码）转换成另一个二进制码，例如常规二进制，反之亦然。 光耦合器包括发光二极管和相关的光电晶体管，它们与缓冲放大器的输出电路关系唯一地连接以实现期望的代码转换。