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1.
公开(公告)号:US07676733B2
公开(公告)日:2010-03-09
申请号:US11325765
申请日:2006-01-04
IPC分类号: H03M13/00
CPC分类号: H04L1/0043 , G06F11/10 , H03M13/33 , H03M13/63 , H03M13/6312 , H04L1/0041 , H04L1/0042 , H04L1/0047 , H04L1/0057 , H04L1/0058 , H04L1/0072 , H04L7/041 , Y02D30/32
摘要: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.
摘要翻译: 描述了用于执行电背板的前向纠错的技术。 一种装置包括具有前向纠错子层的物理层单元,以使用单个位执行前向纠错来表示两位同步头。
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公开(公告)号:US20080250304A1
公开(公告)日:2008-10-09
申请号:US10572116
申请日:2005-09-07
申请人: Andrei Ovchinnikov , Evguenii Krouk
发明人: Andrei Ovchinnikov , Evguenii Krouk
CPC分类号: H03M13/118 , H03M13/1102 , H03M13/618
摘要: Code shortening techniques are used to achieve a variety of code lengths and code rates for Euclidean geometry low density parity check (EG-LDPC) codes.
摘要翻译: 代码缩短技术用于实现欧几里得几何低密度奇偶校验(EG-LDPC)码的各种码长和码率。
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3.
公开(公告)号:US08352828B2
公开(公告)日:2013-01-08
申请号:US13348341
申请日:2012-01-11
IPC分类号: H03M13/00
CPC分类号: H04L1/0043 , G06F11/10 , H03M13/33 , H03M13/63 , H03M13/6312 , H04L1/0041 , H04L1/0042 , H04L1/0047 , H04L1/0057 , H04L1/0058 , H04L1/0072 , H04L7/041 , Y02D30/32
摘要: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may include a physical layer unit having a forward error correction sublayer to perform forward error correction.
摘要翻译: 描述了用于执行电背板的前向纠错的技术。 装置可以包括具有前向纠错子层以执行前向纠错的物理层单元。
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4.
公开(公告)号:US08108756B2
公开(公告)日:2012-01-31
申请号:US12964271
申请日:2010-12-09
IPC分类号: H03M13/00
CPC分类号: H04L1/0043 , G06F11/10 , H03M13/33 , H03M13/63 , H03M13/6312 , H04L1/0041 , H04L1/0042 , H04L1/0047 , H04L1/0057 , H04L1/0058 , H04L1/0072 , H04L7/041 , Y02D30/32
摘要: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.
摘要翻译: 描述了用于执行电背板的前向纠错的技术。 一种装置包括具有前向纠错子层的物理层单元,以使用单个位执行前向纠错来表示两位同步头。
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5.
公开(公告)号:US07873892B2
公开(公告)日:2011-01-18
申请号:US12639797
申请日:2009-12-16
IPC分类号: H03M13/00
CPC分类号: H04L1/0043 , G06F11/10 , H03M13/33 , H03M13/63 , H03M13/6312 , H04L1/0041 , H04L1/0042 , H04L1/0047 , H04L1/0057 , H04L1/0058 , H04L1/0072 , H04L7/041 , Y02D30/32
摘要: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.
摘要翻译: 描述了用于执行电背板的前向纠错的技术。 一种装置包括具有前向纠错子层的物理层单元,以使用单个位执行前向纠错来表示两位同步头。
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6.
公开(公告)号:US20120110421A1
公开(公告)日:2012-05-03
申请号:US13348341
申请日:2012-01-11
IPC分类号: H03M13/00
CPC分类号: H04L1/0043 , G06F11/10 , H03M13/33 , H03M13/63 , H03M13/6312 , H04L1/0041 , H04L1/0042 , H04L1/0047 , H04L1/0057 , H04L1/0058 , H04L1/0072 , H04L7/041 , Y02D30/32
摘要: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed
摘要翻译: 描述了用于执行电背板的前向纠错的技术。 装置可以包括具有前向纠错子层的物理层单元,以使用单个位来执行前向纠错来表示两位同步头。 描述和要求保护其他实施例
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7.
公开(公告)号:US20100095185A1
公开(公告)日:2010-04-15
申请号:US12639797
申请日:2009-12-16
CPC分类号: H04L1/0043 , G06F11/10 , H03M13/33 , H03M13/63 , H03M13/6312 , H04L1/0041 , H04L1/0042 , H04L1/0047 , H04L1/0057 , H04L1/0058 , H04L1/0072 , H04L7/041 , Y02D30/32
摘要: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed.
摘要翻译: 描述了用于执行电背板的前向纠错的技术。 装置可以包括具有前向纠错子层的物理层单元,以使用单个位来执行前向纠错来表示两位同步头。 描述和要求保护其他实施例。
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公开(公告)号:US20070300136A1
公开(公告)日:2007-12-27
申请号:US11472833
申请日:2006-06-21
IPC分类号: H03M13/00
CPC分类号: H03M13/157
摘要: A technique to perform fast decoding of a Reed-Solomon code. A first multiplier unit multiplies a matrix Bh with a column vector v using common adders to produce a column vector v1. The vector v represents one of an error locator polynomial, an error evaluator polynomial, and a derivative polynomial for a (n, k) Reed-Solomon code. The matrix Bh is over GF(2) including first h columns of a matrix B. A second multiplier unit multiplies non-unity components of a column vector A with non-zero components of the column vector v1 component-wise in GF(q) to produce a column vector v2, q being equal to n+1. A third multiplier unit multiplies diagonal sub-matrices of a matrix C with corresponding components of the column vector v2 in GF(2) to produce a column vector v3.
摘要翻译: 执行里德 - 所罗门码快速解码的技术。 第一乘法器单元使用公共加法器将矩阵B
H>与列向量v相乘以产生列向量v 1。 向量v表示(n,k)里德 - 所罗门码的误差定位多项式,误差评估多项式和微分多项式之一。 矩阵B SUP>在包括矩阵B的第一h列的GF(2)上。第二乘法器单元将列向量A的非一致分量与列向量v的非零分量相乘 在GF(q)中1分量,以产生列向量v 2,q等于n + 1。 第三乘法器单元将GF(2)中的矩阵C的对角子矩阵与列向量v 2的对应分量相乘以产生列向量v 3。 -
9.
公开(公告)号:US20110138250A1
公开(公告)日:2011-06-09
申请号:US12964271
申请日:2010-12-09
CPC分类号: H04L1/0043 , G06F11/10 , H03M13/33 , H03M13/63 , H03M13/6312 , H04L1/0041 , H04L1/0042 , H04L1/0047 , H04L1/0057 , H04L1/0058 , H04L1/0072 , H04L7/041 , Y02D30/32
摘要: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed
摘要翻译: 描述了用于执行电背板的前向纠错的技术。 装置可以包括具有前向纠错子层的物理层单元,以使用单个位来执行前向纠错来表示两位同步头。 描述和要求保护其他实施例
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公开(公告)号:US07685503B2
公开(公告)日:2010-03-23
申请号:US11472833
申请日:2006-06-21
IPC分类号: H03M13/00
CPC分类号: H03M13/157
摘要: A technique to perform fast decoding of a Reed-Solomon code. A first multiplier unit multiplies a matrix Bh with a column vector v using common adders to produce a column vector v1. The vector v represents one of an error locator polynomial, an error evaluator polynomial, and a derivative polynomial for a (n, k) Reed-Solomon code. The matrix Bh is over GF(2) including first h columns of a matrix B. A second multiplier unit multiplies non-unity components of a column vector A with non-zero components of the column vector v1 component-wise in GF(q) to produce a column vector v2, q being equal to n+1. A third multiplier unit multiplies diagonal sub-matrices of a matrix C with corresponding components of the column vector v2 in GF(2) to produce a column vector v3.
摘要翻译: 执行里德 - 所罗门码快速解码的技术。 第一乘法器单元使用公共加法器将矩阵Bh与列向量v相乘以产生列向量v1。 向量v表示(n,k)里德 - 所罗门码的误差定位多项式,误差评估多项式和微分多项式之一。 矩阵Bh在包括矩阵B的第一h列的GF(2)之上。第二乘法器单元将GF向上的列向量A的非一个分量与列向量v1的非零分量相乘, 以产生列向量v2,q等于n + 1。 第三乘法器单元将矩阵C的对角子矩阵与GF(2)中的列向量v2的相应分量相乘以产生列向量v3。
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