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公开(公告)号：US20050204121A1
公开(公告)日：2005-09-15
申请号：US10798890
申请日：2004-03-12
申请人： Andrew Burdass
发明人： Andrew Burdass
CPC分类号： G06F9/3861 , G06F9/3804
摘要： An integrated circuit processor core 4 is provided with an instruction pipeline 20 along which program instructions advance. When an exception condition occurs part way through execution of a particular program instruction, then a prefetch of the exception handling program instruction corresponding to that exception is initiated before the currently executing program instruction has completed. In this way the exception handling program instruction is more rapidly available to start the exception processing. The early prefetch may involve performing a lookup in a cache memory 6 and any necessay linefill upon a miss. In addition, the exception handling program instruction amy also be fed into the instruction pipeline 20 before an instruction boundary is reached.
摘要翻译： 集成电路处理器核心4设有指令管线20，程序指令沿着该指令管线20前进。 当通过执行特定程序指令而发生异常情况时，在当前执行的程序指令完成之前启动与该异常相对应的异常处理程序指令的预取。 以这种方式，异常处理程序指令可以更快速地启动异常处理。 早期预取可以涉及在高速缓冲存储器6中执行查找，并且任何必需的在线错过后的行填充。 此外，在达到指令边界之前，异常处理程序指令amy也被馈送到指令流水线20中。
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2.发明授权Prefetching exception vectors by early lookup exception vectors within a cache memory 有权通过早期查找高速缓存内存中的异常向量来预取异常向量公开(公告)号：US07613911B2
公开(公告)日：2009-11-03
申请号：US10798890
申请日：2004-03-12
申请人： Andrew Burdass
发明人： Andrew Burdass
CPC分类号： G06F9/3861 , G06F9/3804
摘要： An integrated circuit processor core 4 is provided with an instruction pipeline 20 along which program instructions advance. When an exception condition occurs part way through execution of a particular program instruction, then a prefetch of the exception handling program instruction corresponding to that exception is initiated before the currently executing program instruction has completed. In this way the exception handling program instruction is more rapidly available to start the exception processing. The early prefetch may involve performing a lookup in a cache memory 6 and any necessary linefill upon a miss. In addition, the exception handling program instruction amy also be fed into the instruction pipeline 20 before an instruction boundary is reached.
摘要翻译： 集成电路处理器核心4设有指令管线20，程序指令沿着该指令管线20前进。 当通过执行特定程序指令而发生异常情况时，在当前执行的程序指令完成之前启动与该异常相对应的异常处理程序指令的预取。 以这种方式，异常处理程序指令可以更快速地启动异常处理。 早期预取可以包括在高速缓存存储器6中执行查找，并且在错过时执行任何必要的线路填充。 此外，在达到指令边界之前，异常处理程序指令amy也被馈送到指令流水线20中。
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公开(公告)号：US20130219149A1
公开(公告)日：2013-08-22
申请号：US13402280
申请日：2012-02-22
CPC分类号： G06F9/02 , G06F9/3836 , G06F9/3861 , G06F9/3873 , G06F9/3887
摘要： A single instruction multiple data processing pipeline 12 for processing floating point operands includes shared special case handling circuitry 34 for performing any operand dependent special case processing operations. The operand dependent special case processing operations result from special case conditions such as operands that are denormal, an infinity, a not-a-number and a floating point number requiring format conversion. The pipeline 12 may in some embodiments be stalled while the operands requiring special case processing are serially shifted to and from the shared special case handling circuitry 34. In other embodiments the instruction in which the special case condition for an operand arose may be recirculated through the pipeline with permutation circuitry 86, 94 being used to swap the operands between lanes in order to place the operand(s) requiring special case processing operations into the lane containing the shared special case handling circuitry 98.
摘要翻译： 用于处理浮点操作数的单个指令多数据处理流水线12包括用于执行任何操作数相关特殊情况处理操作的共享特殊情况处理电路34。 操作数相关的特殊情况处理操作由特殊情况条件产生，例如需要格式转换的非正常，无穷大，非数字和浮点数的操作数。 在一些实施例中，流水线12可以停止，而需要特殊情况处理的操作数被串行地转移到共享的特殊情况处理电路34。在其他实施例中，操作数的特殊情况条件产生的指令可以通过 具有排列电路86,94的流水线用于交换车道之间的操作数，以便将需要特殊情况处理操作的操作数放置在包含共享特殊情况处理电路98的通道中。
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公开(公告)号：US08250309B2
公开(公告)日：2012-08-21
申请号：US11044260
申请日：2005-01-28
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： A data processor comprising: a control register operable to store a cache control value; and data accessing logic responsive to a data access instruction and to said cache control value to look for data to be accessed in a cache if said cache control value has a predetermined value and not to look for said data to be accessed in said cache if said cache control value does not have said predetermined value.
摘要翻译： 一种数据处理器，包括：控制寄存器，用于存储高速缓存控制值; 以及响应于数据访问指令的数据访问逻辑和所述高速缓存控制值，以在所述高速缓存控制值具有预定值的情况下查找要在高速缓存中访问的数据，并且如果所述高速缓存控制值不是在所述高速缓存中寻找要访问的数据，则 高速缓存控制值不具有所述预定值。
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公开(公告)号：US20050182905A1
公开(公告)日：2005-08-18
申请号：US11044260
申请日：2005-01-28
申请人： Patrick McGlew , Andrew Burdass
发明人： Patrick McGlew , Andrew Burdass
CPC分类号： G06F12/0888
摘要： A data processor comprising: a control register operable to store a cache control value; and data accessing logic responsive to a data access instruction and to said cache control value to look for data to be accessed in a cache if said cache control value has a predetermined value and not to look for said data to be accessed in said cache if said cache control value does not have said predetermined value.
摘要翻译： 一种数据处理器，包括：控制寄存器，用于存储高速缓存控制值; 以及响应于数据访问指令的数据访问逻辑和所述高速缓存控制值，以在所述高速缓存控制值具有预定值的情况下查找要在高速缓存中访问的数据，并且如果所述高速缓存控制值不是在所述高速缓存中寻找要访问的数据，则 高速缓存控制值不具有所述预定值。
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公开(公告)号：US20050182863A1
公开(公告)日：2005-08-18
申请号：US10779807
申请日：2004-02-18
CPC分类号： G06F13/28
摘要： A direct memory access controller for controlling data transfer between a data source and a data destination comprising: a read/write port operable to receive data from said data source via a source bus and to output said received data to said data destination via a destination bus; wherein said direct memory access controller is operable in response to a predetermined number of clock pulses, to control said read/write port to output said received data said predetermined number of clock pulses after having received it. Also a direct memory access controller for controlling data transfer between a data source and a data destination comprising: a single read/write port comprising a read channel operable to receive data from said data source via a read path on a bus and a write channel operable to output said received data to said data destination via a write path on said bus, said read and write channel being operable to perform data reads and writes independently of each other.
摘要翻译： 一种用于控制数据源和数据目的地之间的数据传输的直接存储器访问控制器，包括：读/写端口，用于经由源总线从所述数据源接收数据，并经由目的总线将所述接收的数据输出到所述数据目的地 ; 其中所述直接存储器存取控制器响应于预定数量的时钟脉冲而可操作，以控制所述读/写端口在接收到所述预定数量的时钟脉冲之后输出所述接收数据。 还有一种用于控制数据源和数据目的地之间的数据传输的直接存储器访问控制器，包括：单个读/写端口，其包括读通道，读通道可操作以经由总线上的读路径从所述数据源接收数据， 通过所述总线上的写入路径将所述接收的数据输出到所述数据目的地，所述读取和写入通道可操作以独立于彼此执行数据读取和写入。
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公开(公告)号：US20050138257A1
公开(公告)日：2005-06-23
申请号：US10886576
申请日：2004-07-09
申请人： Andrew Burdass , David Seal
发明人： Andrew Burdass , David Seal
CPC分类号： G06F13/24
摘要： A processor core 4 is provided with an interrupt controller 22 which serves to set an interrupt mask bit F and a hardware control when an interrupt fiq occurs. A masking control signal NMI serves to either allow or prevent the software clearing of the interrupt mask bit F.
摘要翻译： 处理器核心4设置有中断控制器22，其用于设置中断屏蔽位F和发生中断信号时的硬件控制。 屏蔽控制信号NMI用于允许或阻止中断屏蔽位F的软件清零。
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公开(公告)号：US09128531B2
公开(公告)日：2015-09-08
申请号：US13402280
申请日：2012-02-22
CPC分类号： G06F9/02 , G06F9/3836 , G06F9/3861 , G06F9/3873 , G06F9/3887
摘要： A single instruction multiple data processing pipeline 12 for processing floating point operands includes shared special case handling circuitry 34 for performing any operand dependent special case processing operations. The operand dependent special case processing operations result from special case conditions such as operands that are denormal, an infinity, a not-a-number and a floating point number requiring format conversion. The pipeline 12 may in some embodiments be stalled while the operands requiring special case processing are serially shifted to and from the shared special case handling circuitry 34. In other embodiments the instruction in which the special case condition for an operand arose may be recirculated through the pipeline with permutation circuitry 86, 94 being used to swap the operands between lanes in order to place the operand(s) requiring special case processing operations into the lane containing the shared special case handling circuitry 98.
摘要翻译： 用于处理浮点操作数的单个指令多数据处理流水线12包括用于执行任何操作数相关特殊情况处理操作的共享特殊情况处理电路34。 操作数相关的特殊情况处理操作由特殊情况条件产生，例如需要格式转换的非正常，无穷大，非数字和浮点数的操作数。 在一些实施例中，流水线12可以停止，而需要特殊情况处理的操作数被串行地转移到共享的特殊情况处理电路34。在其他实施例中，操作数的特殊情况条件产生的指令可以通过 具有排列电路86,94的流水线用于交换车道之间的操作数，以便将需要特殊情况处理操作的操作数放置在包含共享特殊情况处理电路98的通道中。
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公开(公告)号：US07882293B2
公开(公告)日：2011-02-01
申请号：US10886576
申请日：2004-07-09
申请人： Andrew Burdass , David James Seal
发明人： Andrew Burdass , David James Seal
CPC分类号： G06F13/24
摘要： A processor core 4 is provided with an interrupt controller 22 which serves to set an interrupt mask bit F and a hardware control when an interrupt fiq occurs. A masking control signal NMI serves to either allow or prevent the software clearing of the interrupt mask bit F.
摘要翻译： 处理器核心4设置有中断控制器22，其用于设置中断屏蔽位F和发生中断信号时的硬件控制。 屏蔽控制信号NMI用于允许或阻止中断屏蔽位F的软件清零。
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公开(公告)号：US07328391B2
公开(公告)日：2008-02-05
申请号：US10880618
申请日：2004-07-01
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： A cache memory includes error bits corresponding to each line of data. An error detecting circuit uses these error bits to detect if a soft error has occurred within the data of a cache line. If such an error has occurred, then the line may be refilled from the main memory or some other action taken, such as a write back or generation of a soft error abort signal.
摘要翻译： 高速缓冲存储器包括与每行数据相对应的错误位。 错误检测电路使用这些错误位来检测在高速缓存行的数据内是否发生软错误。 如果发生这样的错误，则可以从主存储器或一些其他动作重新输入该行，例如回写或产生软错误中止信号。
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